From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf33.google.com (mail-qv1-xf33.google.com [IPv6:2607:f8b0:4864:20::f33]) by sourceware.org (Postfix) with ESMTPS id 5534B3858D35 for ; Sun, 25 Jun 2023 08:23:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5534B3858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qv1-xf33.google.com with SMTP id 6a1803df08f44-6300510605bso17053626d6.0 for ; Sun, 25 Jun 2023 01:23:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687681395; x=1690273395; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=akq8hz+VkBME4ByJusSSeXIEV0pqJx3jCAUfW3wmQjk=; b=jLlOYJofESD3vBTtqYI1fHOGtXQSqP3OAdZgOZ7EfidxI2ZVOXF6J4vjwnVxaVN/sW DrtVWzAEGmu2P0hLUXaOIDhbMIKROfjLgr68vBOGQ97LFsQYR/XNzLB7/prrSkkT+03t 9h4xVHs6uVa6u6CrPNKCp7NzesZOI/nETV9HeqaIofYsGxcdJQFCdRxYZ25W1BvFEvUC 9B1HgeaaDS+6R+q6RJ+5X5guj4o/3YYXwfeKWSBHeGaXq4y2qJ3d5mtlEHoQ6ce8KepH F/dorqDzE1feqDQshVYjFzZXRqomDeN/x3iAOjovtrVFKXU8Be16Z7RXF5GSbH/WKI+V uKuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687681395; x=1690273395; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=akq8hz+VkBME4ByJusSSeXIEV0pqJx3jCAUfW3wmQjk=; b=erf/ibIVVFOy/mO5lWOaWdxOZMQmewoLGHBQerLDn8kifKC4YvdoJ3cjQjUxf+iGmI 1xk9QgRHBtXR1PuIEbH8DSFU8hXahOFTXNxIcoYKnJ0WVM+g16teUZa1RvmRmhkHatrX C/dBROgaWGKnHjiRawUuXid7ZXL/mt2teOVkYAor0soN/Q2NtvI6o29eX6CUCLaoa4g0 kbojaHjfDfLwkN30njr75ZYqjV6zpnCoYesLo8X3SQSM6MqdReaVOfkb3O6c3YZcTg96 ehCtsST2hHQ9x+S9dlMOzNttOLTi28TGiPgQvH0NELNYz63GWksxf415+E0QdpMaNNMG sIlQ== X-Gm-Message-State: AC+VfDwuKdHmAnMzjtG5+Xsg8aVMmAJnjzA2odbmq267G8l60SGboQ09 WLAYl1f0kByAxobgiK9pfdK2o0sFrT1/mk8cGsAPMkez X-Google-Smtp-Source: ACHHUZ51sXgdymHeAQ0XKLR6GK6bpapFs3RJh53ATsSsJ7aBpQQEhlc58eN2DK7XcZIFVgvZ/gFvjsDCGAgbMAD/d1Y= X-Received: by 2002:ad4:5fcc:0:b0:631:ec97:cce9 with SMTP id jq12-20020ad45fcc000000b00631ec97cce9mr20019770qvb.63.1687681395598; Sun, 25 Jun 2023 01:23:15 -0700 (PDT) MIME-Version: 1.0 References: <010601d9a6c6$5e1d8a70$1a589f50$@nextmovesoftware.com> In-Reply-To: <010601d9a6c6$5e1d8a70$1a589f50$@nextmovesoftware.com> From: Uros Bizjak Date: Sun, 25 Jun 2023 10:23:04 +0200 Message-ID: Subject: Re: [x86_PATCH] New *ashl_doubleword_highpart define_insn_and_split. To: Roger Sayle Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sat, Jun 24, 2023 at 8:04=E2=80=AFPM Roger Sayle wrote: > > > This patch contains a pair of (related) optimizations in i386.md that > allow us to generate better code for the example below (this is a step > towards fixing a bugzilla PR, but I've forgotten the number). > > __int128 foo64(__int128 x, long long y) > { > __int128 t =3D (__int128)y << 64; > return x ^ t; > } > > The hidden issue is that the RTL currently seen by reload contains > the sign extension of y from DImode to TImode, even though this is > dead (not required) for left shifts by more than WORD_SIZE bits. > > (insn 11 8 12 2 (parallel [ > (set (reg:TI 0 ax [orig:91 y ] [91]) > (sign_extend:TI (reg:DI 1 dx [97]))) > (clobber (reg:CC 17 flags)) > (clobber (scratch:DI)) > ]) {extendditi2} > > What makes this particularly undesirable is that the sign-extension > pattern above requires an additional DImode scratch register, indicated > by the clobber, which unnecessarily increases register pressure. > > The proposed solution is to add a define_insn_and_split for such > left shifts (of sign or zero extensions) that only have a non-zero > highpart, where the extension is redundant and eliminated, that can > be split after reload, without scratch registers or early clobbers. > > This (late split) exposes a second optimization opportunity where > setting the lowpart to zero can sometimes be combined/simplified with > the following instruction during peephole2. > > For the test case above, we previously generated with -O2: > > foo64: xorl %eax, %eax > xorq %rsi, %rdx > xorq %rdi, %rax > ret > > with this patch, we now generate: > > foo64: movq %rdi, %rax > xorq %rsi, %rdx > ret > > Likewise for the related -m32 test case, we go from: > > foo32: movl 12(%esp), %eax > movl %eax, %edx > xorl %eax, %eax > xorl 8(%esp), %edx > xorl 4(%esp), %eax > ret > > to the improved: > > foo32: movl 12(%esp), %edx > movl 4(%esp), %eax > xorl 8(%esp), %edx > ret > > > This patch has been tested on x86_64-pc-linux-gnu with make bootstrap > and make -k check, both with and without --target_board=3Dunix{-m32} > with no new failures. Ok for mainline? > > > 2023-06-24 Roger Sayle > > gcc/ChangeLog > * config/i386/i386.md (peephole2): Simplify zeroing a register > followed by an IOR, XOR or PLUS operation on it, into a move. > (*ashl3_doubleword_highpart): New define_insn_and_split to > eliminate (and hide from reload) unnecessary word to doubleword > extensions that are followed by left shifts by sufficient large > (but valid) bit counts. > > gcc/testsuite/ChangeLog > * gcc.target/i386/ashldi3-1.c: New 32-bit test case. > * gcc.target/i386/ashlti3-2.c: New 64-bit test case. OK. Thanks, Uros. > > > Thanks again, > Roger > -- >