From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 100537 invoked by alias); 20 Jun 2017 05:52:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 100510 invoked by uid 89); 20 Jun 2017 05:52:34 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.0 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-vk0-f49.google.com Received: from mail-vk0-f49.google.com (HELO mail-vk0-f49.google.com) (209.85.213.49) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 20 Jun 2017 05:52:33 +0000 Received: by mail-vk0-f49.google.com with SMTP id y70so63685236vky.3 for ; Mon, 19 Jun 2017 22:52:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=81n1fKnxbVElWsljX7F2h3UZQvtmf/DIQJ9kv7N5bjo=; b=YSQ1y+CJz3Y4E3gG/qy2c4ILssE0Vq3II7QoenzWosdlBwspxKyrVHIme7SnXP2P2k /dSQLx/831UDhmUWr52BB0eg+jlXlkGtvp096r8zmrrQsfLDzi89ogE8KOGBRdxE4NxP AmV5yom37AZaj9m99CeJWJRH6ZudvmhZ9CAhMOBC9aBgIQuoRjb7TREhTwDsCo8W0Ylp DwymazyAs4V2AhEeSFdDZd2kmNGV2PXY536W5oSUtTP0V4P7poZ2PKiOKMT/cyn/qCQH /56DUSKl6gCrn8TrA2m2cRgivgQQyk0L9LrCi4Q4Btaq5Cy4rumJ8FirpgV0IGalzvIq RNhw== X-Gm-Message-State: AKS2vOydYKVTov4HFvv95mwwmpreqIUbgRCbbbGtidFrLS0A6fxxzq6u 34fUbqztlhPT40psVzFLqx8HXHIu+Q== X-Received: by 10.31.63.207 with SMTP id m198mr15654511vka.82.1497937951424; Mon, 19 Jun 2017 22:52:31 -0700 (PDT) MIME-Version: 1.0 Received: by 10.103.69.29 with HTTP; Mon, 19 Jun 2017 22:52:30 -0700 (PDT) In-Reply-To: <20170619153730.GT2123@tucnak> References: <20170619153730.GT2123@tucnak> From: Uros Bizjak Date: Tue, 20 Jun 2017 05:52:00 -0000 Message-ID: Subject: Re: [PATCH] Fix x86 ICE with -mtune=amdfam10 -mno-sse2 (PR target/81121) To: Jakub Jelinek Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2017-06/txt/msg01392.txt.bz2 On Mon, Jun 19, 2017 at 5:37 PM, Jakub Jelinek wrote: > Hi! > > This testcase started to ICE when PR70873 fix changed the splitter: > @@ -5153,11 +5147,11 @@ > ;; slots when !TARGET_INTER_UNIT_MOVES_TO_VEC disables the general_regs > ;; alternative in sse2_loadld. > (define_split > - [(set (match_operand:MODEF 0 "register_operand") > + [(set (match_operand:MODEF 0 "sse_reg_operand") > (float:MODEF (match_operand:SI 1 "nonimmediate_operand")))] > - "TARGET_SSE2 && TARGET_SSE_MATH > - && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) > - && reload_completed && SSE_REG_P (operands[0]) > + "TARGET_USE_VECTOR_CONVERTS > + && optimize_function_for_speed_p (cfun) > + && reload_completed > && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC) > && (!EXT_REX_SSE_REG_P (operands[0]) > || TARGET_AVX512VL)" > Having sse_reg_operand match the output operand does not imply > TARGET_SSE2 is enabled, but we need it for both the > if (mode == V4SFmode) > emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4])); > else > emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4])); > instructions that we want to use in the splitter. > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk > (or do you want TARGET_SSE2 first or right after > TARGET_USE_VECTOR_CONVERTS)? Please put TARGET_SSE2 first in the insn condition. > 2017-06-19 Jakub Jelinek > > PR target/81121 > * config/i386/i386.md (TARGET_USE_VECTOR_CONVERTS float si->{sf,df} > splitter): Require TARGET_SSE2 in the condition. > > * gcc.target/i386/pr81121.c: New test. OK with the above change. Thanks, Uros. > --- gcc/config/i386/i386.md.jj 2017-06-08 20:50:46.000000000 +0200 > +++ gcc/config/i386/i386.md 2017-06-19 11:30:38.937491668 +0200 > @@ -5294,6 +5294,7 @@ (define_split > && optimize_function_for_speed_p (cfun) > && reload_completed > && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC) > + && TARGET_SSE2 > && (!EXT_REX_SSE_REG_P (operands[0]) > || TARGET_AVX512VL)" > [(const_int 0)] > --- gcc/testsuite/gcc.target/i386/pr81121.c.jj 2017-06-19 11:36:06.545501324 +0200 > +++ gcc/testsuite/gcc.target/i386/pr81121.c 2017-06-19 11:35:40.000000000 +0200 > @@ -0,0 +1,10 @@ > +/* PR target/81121 */ > +/* { dg-do compile } */ > +/* { dg-options "-O0 -march=amdfam10 -mno-sse2" } */ > + > +void > +foo (short *x, short *y) > +{ > + float a = 0; > + y[0] = x[0] * a; > +} > > Jakub