From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by sourceware.org (Postfix) with ESMTPS id AD49A3858D32 for ; Mon, 13 Nov 2023 11:25:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AD49A3858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org AD49A3858D32 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::130 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699874757; cv=none; b=F2nONYyn0I+wlimDYYu3YclE01tePaHLrrPJSQxeWecIwOl22cu79GXp2Ylj0RUOe1q0D6u3BhmvMQnFOuOQkk5RKf6eK23G3czlA9f2D+Y2NXJLZc6cF31dGrGfGXimZclf3pWeNN+bNREObQXDtpaI4GQ1JEkSYGG2IHqf0/w= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699874757; c=relaxed/simple; bh=BJ454O4zcxStk/JqlBWg4quIkUMrW8Rjo2GWsjCFgmE=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=or1C9clpHTO93vW4NJ0p04+gtNdf8peuiy/B9rOH3z1dgqr4MlCsIo2OYRDZeWU4o3DcXl+qVeUGzGoe654lIA8OnGlPRpo4drHdNW2WEUU2THZeBK4FYqQo8QXoYo26sV5k/9XqkZNXGWzUy40ZvgwRXad/faGFW3LjYGMhba0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-507e85ebf50so5619839e87.1 for ; Mon, 13 Nov 2023 03:25:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1699874754; x=1700479554; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=Pqh/srQ9TjD+F4O1qwM7Uve5zXP7ISYSP+R82+V+yHA=; b=nG0KcilAB3TwCZHpOkFOL3I21GFutfFTx+/25OVbYm1F1iKwBBo+GhLi5m6p6VgUqk zHkHSEhjpTLxEjENu+D0J8ToKaTKG29kl5mjJvfRCfgrCDSIWC4g9v0Jt4619LPYgwQM 1Gx9Nj7qqFsf+cJB42uB3cZD2t83vJgdazNdhFKV7m8nFALzKxyeEUqB2W3N5q0g3j8w PFa9xhCulcVMBRRSYGryGJgWg64ULDUC+LfUMWPI8wLWAxy8jTTb7aGfW1unCbjbIPsx MqxWykalgyC1LSqLxXA3q/tcDynLdGx+9exYsYoLzGbpW85Wxvw4jUeLqL30zZitdmHP maSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699874754; x=1700479554; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Pqh/srQ9TjD+F4O1qwM7Uve5zXP7ISYSP+R82+V+yHA=; b=uHc+SVpulpK+peaKwXxsGyurLD3/AxFf76MSvWbj8MPwBFTVQ8PCWxnT7YIYNe+agS 0UlmHtN5AL1W11jByTIdEs/IEu27lnKuKMHYa83hHU8qcnZPF63cAXrYCXDkRihbQ3lU zsmMxm4oRCpMptZRqrAc5RY0j+hr3HLjVQJk5L8EKvvOyHiq+DXACj1SO16amT7IUS/P 4GXfsnN1vloj0mJndOrIUCSB6geccB/p7kRp85gbV2+gIM3kTQoZnxWjjB15gw4+2Auy suaQmubAN1lcyE2LZw0S9LxqqssjxK1OVd4fZBy4nXgmY9Nhd5IpsT/KPjD7kaLw4rKz wgyA== X-Gm-Message-State: AOJu0Yw+fGLLxLO4CYTUVxXQsSkgT4yLkus1hm8HCPh+zm0GnKY31x0D x8Wg2Rm9IJm2lebp+bGrp4jj4VtQOOrUlxDgxST92WkeNKE= X-Google-Smtp-Source: AGHT+IHe5rvD9+YHWRKc6XxkAcDa3WEDL5DeMaK5tSORh4fTUJcbgyqX81Ufheio+5AGAkj2hGMtmZIJfHvPOyOb8n0= X-Received: by 2002:a05:6512:4014:b0:500:7a21:3e78 with SMTP id br20-20020a056512401400b005007a213e78mr5256309lfb.55.1699874753826; Mon, 13 Nov 2023 03:25:53 -0800 (PST) MIME-Version: 1.0 References: <20231110014158.371690-1-haochen.jiang@intel.com> In-Reply-To: From: Richard Biener Date: Mon, 13 Nov 2023 12:25:41 +0100 Message-ID: Subject: Re: [RFC] Intel AVX10.1 Compiler Design and Support To: Hongtao Liu Cc: Haochen Jiang , gcc-patches@gcc.gnu.org, hongtao.liu@intel.com, ubizjak@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Nov 13, 2023 at 7:58=E2=80=AFAM Hongtao Liu wr= ote: > > On Fri, Nov 10, 2023 at 6:15=E2=80=AFPM Richard Biener > wrote: > > > > On Fri, Nov 10, 2023 at 2:42=E2=80=AFAM Haochen Jiang wrote: > > > > > > Hi all, > > > > > > This RFC patch aims to add AVX10.1 options. After we added -m[no-]eve= x512 > > > support, it makes a lot easier to add them comparing to the August ve= rsion. > > > Detail for AVX10 is shown below: > > > > > > Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specif= ication > > > It describes the Intel Advanced Vector Extensions 10 Instruction Set > > > Architecture. > > > https://cdrdv2.intel.com/v1/dl/getContent/784267 > > > > > > The Converged Vector ISA: Intel Advanced Vector Extensions 10 Technic= al Paper > > > It provides introductory information regarding the converged vector I= SA: Intel > > > Advanced Vector Extensions 10. > > > https://cdrdv2.intel.com/v1/dl/getContent/784343 > > > > > > Our proposal is to take AVX10.1-256 and AVX10.1-512 as two "virtual" = ISAs in > > > the compiler. AVX10.1-512 will imply AVX10.1-256. They will not enabl= e > > > anything at first. At the end of the option handling, we will check w= hether > > > the two bits are set. If AVX10.1-256 is set, we will set the AVX512 r= elated > > > ISA bits. AVX10.1-512 will further set EVEX512 ISA bit. > > > > > > It means that AVX10 options will be separated from the existing AVX51= 2 and the > > > newly added -m[no-]evex512 options. AVX10 and AVX512 options will con= trol > > > (enable/disable/set vector size) the AVX512 features underneath indep= endently. > > > If there=E2=80=99s potential overlap or conflict between AVX10 and AV= X512 options, > > > some rules are provided to define the behavior, which will be describ= ed below. > > > > > > avx10.1 option will be provided as an alias of avx10.1-256. > > > > > > In the future, the AVX10 options will imply like this: > > > > > > AVX10.1-256 <---- AVX10.1-512 > > > ^ ^ > > > | | > > > > > > AVX10.2-256 <---- AVX10.2-512 > > > ^ ^ > > > | | > > > > > > AVX10.3-256 <---- AVX10.3-512 > > > ^ ^ > > > | | > > > > > > Each of them will have its own option to enable/disabled correspondin= g > > > features. The alias avx10.x will also be provided. > > > > > > As mentioned in August version RFC, since we lean towards the adoptio= n of > > > AVX10 instead of AVX512 from now on, we don=E2=80=99t recommend users= to combine the > > > AVX10 and legacy AVX512 options. > > > > I wonder whether adoption could be made easier by also providing a > > -mavx10[.0] level that removes some of the more obscure sub-ISA require= ments > > to cover more existing implementations (I'd not add -mavx10.0-512 here)= . > > I'd require only skylake-AVX512 features here, basically all non-KNL AV= X512 > > CPUs should have a "virtual" AVX10 level that allows to use that featur= e set, > We have -mno-evex512 can cover those cases, so what you want is like a > simple alias of "-march=3Dskylake-avx512 -mno-evex512"? For the AVX512 enabled sub-isas of skylake-avx512 yes I guess. > > restricted to 256bits so future AVX10-256 implementations can handle it > > as well as all existing (and relevant, which excludes KNL) AVX512 > > implementations. > > > > Otherwise AVX10 is really a hard sell (as AVX512 was originally). > It's a rebranding of the existing AVX512 to AVX10, AVX10.0 just > complicated things further(considering we already have x86-64-v4 which > is different from skylake-avx512). Well, the cut-off for "AVX512" is quite arbitrary. Introducing a "new" ISA that's only available in HW available in the future and suggesting users to embrac= e that already (like Intel did with AVX512 without offering client SKU suppor= t) is a hard sell. I realize Intel thinks client SKU support for AVX10 (restricted to 256bit) = will be "easier". But then don't expect anybody to adopt that in the next 10 ye= ars. Just to add - we were suggesting to use x86_64-v3 for the "next" enterprise product but got downvoted to x86_64-v2 for compatibility reasons. If it were possible I'd axe x86_64-v4. Maybe we should add a x86_64-v3.5 that sits inbetween v3 and v4, offering AVX512 but restricted to 256bit (and obviously not requiring more of the AVX512 features that v4 requires). Richard. > > > > > However, we would like to introduce some > > > simple rules for user when it comes to combination. > > > > > > 1. Enabling AVX10 and AVX512 at the same command line with different = vector > > > size will lead to a warning message. The behavior of the compiler wil= l be > > > enabling AVX10 with longer, i.e., 512 bit vector size. > > > > > > If the vector sizes are the same (e.g. -mavx10.1-256 -mavx512f -mno-e= vex512, > > > -mavx10.1-512 -mavx512f), it will be valid with the corresponding vec= tor size. > > > > > > 2. -mno-avx10.1 option can=E2=80=99t disable any features enabled by = AVX512 options or > > > impact the vector size, and vice versa. The compiler will emit warnin= gs if > > > necessary. > > > > > > For the auto dispatch support including function multi versioning, fu= nction > > > attribute usage, the behavior will be identical to compiler options. > > > > > > If you have any questions, feel free to ask in this thread. > > > > > > Thx, > > > Haochen > > > > > > > > > > -- > BR, > Hongtao