From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by sourceware.org (Postfix) with ESMTPS id 1CA7D3858C56 for ; Tue, 27 Feb 2024 09:47:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1CA7D3858C56 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1CA7D3858C56 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::132 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709027277; cv=none; b=QITOy8QWUx7AVKRVoFV/D9f4Ojjxc+PQnpS3Tf0bykoLdJMNBHFZrafsjPH6XiEOIySeBpN6Y6yMSt5VFZi6shcO+LmvwHU2Iyjum+obNKOD2UF06k8i/Jd2rix1B0ZIWmB1IQ8sFMno/GN3zJHqrjdMZWvm4+sVvkJ3VpUyaCg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709027277; c=relaxed/simple; bh=9kfKskn5RYCt0ylA6LtH+AIWL7cRIMPtclwLAhaj53I=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=VQaXn5GvXmPVCevC+WwZD/pEGAlWMc1BR5J6pr1wvJEc7nrRwYXD7Bp4jk+egwioOVqP7+JB3bd7JIg4vZ2tBZhHoOaC3c7ABz2ywfFIkY190DGN+c6ZcmMWno3CxpWknLNAF1YzqflUJfFxo2StrDCseZtqysUhCKJQm+WyWDo= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-5131316693cso238819e87.0 for ; Tue, 27 Feb 2024 01:47:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1709027265; x=1709632065; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=1SlzsD2idEb2yofWIjGHs06H9KA9PZ9D3AWCzSiUjMo=; b=DZd1q7xiFztb4icAHB/BPuxB91/h0Kz/6Vp56p+ycHsIpNCQJOw7VRPwJnX3LUkjOW uNPrg2dIdrzO89buoPuoinWUFhWLBoKGsrwtj8DqnTut3T9Qmwc9J7fybq0XmeEQ/Z01 cARcyKGa8wEYi96b/1i3rFzoEmGaYYq1ljjHiSVE6a6GZMczztDO3PCAe5HYtvKZL5mK 97zM7BxQ46w4ByGRmTAZAh7q0uwo44Ry3v9N02qD5eacat0BuUXjbA8XgZnuL4pO5juO Uei+MQF/AEUm7GgkLvTf0yYoeZAELE05UAFCvQSNyzxuOIUk0bfhhQf2y4lkiHX+V00B 9isw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709027265; x=1709632065; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1SlzsD2idEb2yofWIjGHs06H9KA9PZ9D3AWCzSiUjMo=; b=frYGOoQzvBBLt1pKb4y6MlQ4SHZawSC+IYo/e/k/tfL6/UOgCIUMRZWjG1r/61FT2X YlJv+MPTHQYuol3fQeq4bONcX9Hn5MYpy6DiQ6MJfCqn3bYa/zzonHgyQIrkRrnYYMxZ kjFCXlz8YQ98+IRNIQhl6bWViIvK/MjRRstqHWoYK8GKIntWt8hRPPsU090Y4beymYBF RXcMFAsESCpkSfiZqH1K8pk1fmOdz0j2qTIKHE3Wt1bRZarb4fvwc0+z2uLnkZjN0gn+ vVxdiKM2MTrlvo2093e50gjSb6heTJC5i8rj/kutkfk7lpLzQ7AF0UXZYBK00Nv1iRbU QjkQ== X-Gm-Message-State: AOJu0YyPtbUojijBPZyanYdAUHq+LUTFDvgDAuHGIFik/1ESq5mPEEFG Dz2s6+qG0wo1UK7fgt+7fj48hMtq2AYBAj0Tp7pfSGKF9safmjf346g4Re8gSpxjs0n7aeqNNvj 1vaZ8VhX0VJGvYeXF3ZTKXjqGSB8= X-Google-Smtp-Source: AGHT+IFM1C1P8Up5IWHvkwmqDCTnnExjhxvs1nZ/zQ6TkVHhNSkHKFMmgRHvenE07qOd2sBiJ5mBWRwKzf6dTMWY10E= X-Received: by 2002:ac2:43d6:0:b0:512:cb9f:b279 with SMTP id u22-20020ac243d6000000b00512cb9fb279mr5398051lfl.66.1709027265486; Tue, 27 Feb 2024 01:47:45 -0800 (PST) MIME-Version: 1.0 References: <20240226032558.587912-1-pan2.li@intel.com> <20240226142235.3215553-1-pan2.li@intel.com> In-Reply-To: <20240226142235.3215553-1-pan2.li@intel.com> From: Richard Biener Date: Tue, 27 Feb 2024 10:47:34 +0100 Message-ID: Subject: Re: [PATCH v2] DSE: Bugfix ICE after allow vector type in get_stored_val To: pan2.li@intel.com, Richard Sandiford , Jeff Law Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, yanzhang.wang@intel.com, rdapp.gcc@gmail.com, hongtao.liu@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Feb 26, 2024 at 3:22=E2=80=AFPM wrote: > > From: Pan Li > > We allowed vector type for get_stored_val when read is less than or > equal to store in previous. Unfortunately, we missed to adjust the > validate_subreg part accordingly. When the vector type's size is > less than vector register, it will be considered as invalid in the > validate_subreg. > > Consider the validate_subreg is kind of a can with worms and we are > in stage 4. We will fix the issue from the DES side, and make sure > the subreg is valid for both the read_mode and store_mode before > perform the real gen_lowpart. > > The below test are passed for this patch: > > * The x86 bootstrap test. > * The x86 regression test. > * The riscv regression test. > * The aarch64 regression test. > > gcc/ChangeLog: > > * dse.cc (get_stored_val): Add validate_subreg check before > perform the gen_lowpart for rtl. > > gcc/testsuite/ChangeLog: > > * gcc.dg/tree-ssa/ssa-fre-44.c: Add compile option to trigger > the ICE. > * gcc.target/riscv/rvv/base/bug-6.c: New test. > > Signed-off-by: Pan Li > --- > gcc/dse.cc | 4 +++- > gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c | 2 +- > .../gcc.target/riscv/rvv/base/bug-6.c | 22 +++++++++++++++++++ > 3 files changed, 26 insertions(+), 2 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c > > diff --git a/gcc/dse.cc b/gcc/dse.cc > index edc7a1dfecf..1596da91da0 100644 > --- a/gcc/dse.cc > +++ b/gcc/dse.cc > @@ -1946,7 +1946,9 @@ get_stored_val (store_info *store_info, machine_mod= e read_mode, > copy_rtx (store_info->const_rhs)); > else if (VECTOR_MODE_P (read_mode) && VECTOR_MODE_P (store_mode) > && known_le (GET_MODE_BITSIZE (read_mode), GET_MODE_BITSIZE (store_m= ode)) > - && targetm.modes_tieable_p (read_mode, store_mode)) > + && targetm.modes_tieable_p (read_mode, store_mode) > + && validate_subreg (read_mode, store_mode, copy_rtx (store_info->rhs= ), > + subreg_lowpart_offset (read_mode, store_mode))) > read_reg =3D gen_lowpart (read_mode, copy_rtx (store_info->rhs)); Thanks for the 2nd try. I'll note the above uses gen_lowpart but validate_subreg which is sort-of a mismatch? But I'll leave this for review to people with= more knowledge in this area. Jeff? Richard? Thanks, Richard. > else > read_reg =3D extract_low_bits (read_mode, store_mode, > diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c b/gcc/testsuite/g= cc.dg/tree-ssa/ssa-fre-44.c > index f79b4c142ae..624a00a4f32 100644 > --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c > +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O -fdump-tree-fre1" } */ > +/* { dg-options "-O -fdump-tree-fre1 -O3 -ftree-vectorize" } */ > > struct A { float x, y; }; > struct B { struct A u; }; > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c b/gcc/testsu= ite/gcc.target/riscv/rvv/base/bug-6.c > new file mode 100644 > index 00000000000..5bb00b8f587 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c > @@ -0,0 +1,22 @@ > +/* Test that we do not have ice when compile */ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d -O3 -ftree-vectorize" } = */ > + > +struct A { float x, y; }; > +struct B { struct A u; }; > + > +extern void bar (struct A *); > + > +float > +f3 (struct B *x, int y) > +{ > + struct A p =3D {1.0f, 2.0f}; > + struct A *q =3D &x[y].u; > + > + __builtin_memcpy (&q->x, &p.x, sizeof (float)); > + __builtin_memcpy (&q->y, &p.y, sizeof (float)); > + > + bar (&p); > + > + return x[y].u.x + x[y].u.y; > +} > -- > 2.34.1 >