From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 109206 invoked by alias); 24 Sep 2019 11:29:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 109198 invoked by uid 89); 24 Sep 2019 11:29:53 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy=H*i:sk:mptimpi, H*f:sk:mptimpi X-HELO: mail-lf1-f50.google.com Received: from mail-lf1-f50.google.com (HELO mail-lf1-f50.google.com) (209.85.167.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 24 Sep 2019 11:29:51 +0000 Received: by mail-lf1-f50.google.com with SMTP id t8so1107973lfc.13 for ; Tue, 24 Sep 2019 04:29:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=8n7iN7dGEUaXH7AofxFLI22i+GZO1s1+t+kweqxXWQM=; b=LHTVuujS6j665HD4KoRJp0dCn26D6Tv/V7Hz1QBDVRdx/+tVFOPtlHXUtb7MHlMxuo lmdXOOAMifwC4q7SzLkqYgL67kYbE0IkD4H4YGPHeQfkzitUWszRAdAApB04TV2jh0w/ Kz6ABR4az8an6rehbkRVIhYPHIfjB7ku0tGB/H9MfboDV7bA2v97XRdbCcc5pG6GIfrT tMmR1mTQUfr8IZ8rgpvEJfA0Exn7nkwGQEBc/6G3zEBbSG8XVarDfIPqMwdc/H5Lklxk esrUg20mU8Yn1lEpboab0TOIOTRTfwyGV0oOgevG7VxK2m25Mm2nADlbDCf/qsVZksk2 cyng== MIME-Version: 1.0 References: <366dfa22-58e7-e1df-62c3-cc98082a552c@suse.cz> In-Reply-To: From: Richard Biener Date: Tue, 24 Sep 2019 11:29:00 -0000 Message-ID: Subject: Re: [PATCH][RFC] Come up with VEC_COND_OP_EXPRs. To: Richard Sandiford Cc: =?UTF-8?Q?Martin_Li=C5=A1ka?= , GCC Patches Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2019-09/txt/msg01384.txt.bz2 On Tue, Sep 24, 2019 at 1:11 PM Richard Sandiford wrote: > > Martin Li=C5=A1ka writes: > > Hi. > > > > The patch introduces couple of new TREE_CODEs that will help us to have > > a proper GIMPLE representation of current VECT_COND_EXPR. Right now, > > the first argument is typically a GENERIC tcc_expression tree with 2 op= erands > > that are visited at various places in GIMPLE code. That said, based on = the discussion > > with Richi, I'm suggesting to come up with e.g. > > VECT_COND_LT_EXPR. Such a c= hange logically > > introduces new GIMPLE_QUATERNARY_RHS gassignments. For now, the VEC_CON= D_EXPR remains > > and is only valid in GENERIC and gimplifier will take care of the corre= sponding transition. > > > > The patch is a prototype and missing bits are: > > - folding support addition for GIMPLE_QUATERNARY_RHS is missing > > - fancy tcc_comparison expressions like LTGT_EXPR, UNORDERED_EXPR, ORDE= RED_EXPR, > > UNLT_EXPR and others are not supported right now > > - comments are missing for various functions added > > > > Apart from that I was able to bootstrap and run tests with a quite smal= l fallout. > > Thoughts? > > Martin > > I think this is going in the wrong direction. There are some targets > that can only handle VEC_COND_EXPRs well if we know the associated > condition, and others where a compare-and-VEC_COND_EXPR will always be > two operations. In that situation, it seems like the native gimple > representation should be the simpler representation rather than the > more complex one. That way the comparisons can be optimised > independently of any VEC_COND_EXPRs on targets that benefit from that. > > So IMO it would be better to use three-operand VEC_COND_EXPRs with > no embedded conditions as the preferred gimple representation and > have internal functions for the fused operations that some targets > prefer. This means that using fused operations is "just" an instruction > selection decision rather than hard-coded throughout gimple. (And that > fits in well with the idea of doing more instruction selection in gimple.) So I've been doing that before, but more generally also for COND_EXPR. We cannot rely on TER and the existing RTL expansion "magic" for the instruction selection issue you mention because TER isn't reliable. With IFNs for optabs we could do actual [vector] condition instruction selection before RTL expansion, ignoring "single-use" issues - is that what you are hinting at? How should the vectorizer deal with this? Should it directly use the optab IFNs then when facing "split" COND_EXPRs? IIRC the most fallout of a simple patch (adjusting is_gimple_condexpr) is in the vectorizer. Note I'm specifically looking for a solution that applies to both COND_EXPR and VEC_COND_EXPR since both suffer from the same issues. There was also recent work in putting back possibly trapping comparisons into [VEC_]COND_EXPR because it doesn't interfere with EH and allows better code. Also you SVE people had VN issues with cond-exprs and VN runs into the exact same issue (but would handle separate comparisons better - with the caveat of breaking TER). Richard. > > Thanks, > Richard