From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7258 invoked by alias); 25 Jul 2011 09:40:02 -0000 Received: (qmail 7243 invoked by uid 22791); 25 Jul 2011 09:40:01 -0000 X-SWARE-Spam-Status: No, hits=-2.2 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-gy0-f175.google.com (HELO mail-gy0-f175.google.com) (209.85.160.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 25 Jul 2011 09:39:47 +0000 Received: by gyd12 with SMTP id 12so2446893gyd.20 for ; Mon, 25 Jul 2011 02:39:46 -0700 (PDT) MIME-Version: 1.0 Received: by 10.151.43.19 with SMTP id v19mr4013793ybj.444.1311586786294; Mon, 25 Jul 2011 02:39:46 -0700 (PDT) Received: by 10.150.205.2 with HTTP; Mon, 25 Jul 2011 02:39:45 -0700 (PDT) In-Reply-To: <201107250910.p6P9AeaS014391@d06av02.portsmouth.uk.ibm.com> References: <201107250910.p6P9AeaS014391@d06av02.portsmouth.uk.ibm.com> Date: Mon, 25 Jul 2011 10:08:00 -0000 Message-ID: Subject: Re: [patch] Fix PR tree-optimization/49771 From: Richard Guenther To: Ulrich Weigand Cc: Ira Rosen , gcc-patches@gcc.gnu.org, Patch Tracking Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-07/txt/msg02119.txt.bz2 On Mon, Jul 25, 2011 at 11:10 AM, Ulrich Weigand wrot= e: > Richard Guenther wrote: >> On Sun, Jul 24, 2011 at 2:02 PM, Ira Rosen wrote: >> > On 21 July 2011 15:19, Ira Rosen wrote: >> >> I reproduced the failure. It occurs without Richard's >> >> (http://gcc.gnu.org/ml/gcc-patches/2011-07/msg01022.html) and this >> >> patches too. Obviously the vectorized loop is executed, but at the >> >> moment I don't understand why. I'll have a better look on Sunday. >> > >> > Actually it doesn't choose the vectorized code. But the scalar version >> > gets optimized in a harmful way for SPU, AFAIU. >> > Here is the scalar loop after vrp2 >> > >> > : >> > =A0# ivtmp.42_50 =3D PHI >> > =A0D.4593_42 =3D (void *) ivtmp.53_32; >> > =A0D.4520_33 =3D MEM[base: D.4593_42, offset: 0B]; >> > =A0D.4521_34 =3D D.4520_33 + 1; >> > =A0MEM[symbol: a, index: ivtmp.42_50, offset: 0B] =3D D.4521_34; >> > =A0ivtmp.42_45 =3D ivtmp.42_50 + 4; >> > =A0if (ivtmp.42_45 !=3D 16) >> > =A0 =A0goto ; >> > =A0else >> > =A0 =A0goto ; >> > >> > and the load is changed by dom2 to: >> > >> > : >> > =A0... >> > =A0D.4520_33 =3D MEM[base: vect_pa.9_19, offset: 0B]; >> > =A0 ... >> > >> > where vector(4) int * vect_pa.9; >> > >> > And the scalar loop has no rotate for that load: >> >> Hum. =A0This smells like we are hiding sth from the tree optimizers? > > Well, the back-end assumes a pointer to vector type is always > naturally aligned, and therefore the data it points to can be > accessed via a simple load, with no extra rotate needed. I can't see any use of VECTOR_TYPE in config/spu/, and assuming anything about alignment just because of the kind of the pointer is bogus - the scalar code does a scalar read using that pointer. So the backend better should look at the memory operation, not at the pointer type. That said, I can't find any code that looks suspicious in the spu backend. > It seems what happened here is that somehow, a pointer to int > gets replaced by a pointer to vector, even though their alignment > properties are different. No, they are not. They get replaced if they are value-equivalent in which case they are also alignment-equivalent. But well, the dump snippet wasn't complete and I don't feel like building a SPU cross to verify myself. > This vector pointer must originate somehow in the vectorizer, > however, since the original C source does not contain any > vector types at all ... That's for sure true, it must be the initial pointer we then increment in the vectorized loop. Richard. > Bye, > Ulrich > > -- > =A0Dr. Ulrich Weigand > =A0GNU Toolchain for Linux on System z and Cell BE > =A0Ulrich.Weigand@de.ibm.com >