From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24458 invoked by alias); 1 Jun 2017 07:49:06 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 20081 invoked by uid 89); 1 Jun 2017 07:48:40 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.4 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-oi0-f49.google.com Received: from mail-oi0-f49.google.com (HELO mail-oi0-f49.google.com) (209.85.218.49) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 01 Jun 2017 07:48:37 +0000 Received: by mail-oi0-f49.google.com with SMTP id h4so44370974oib.3 for ; Thu, 01 Jun 2017 00:48:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=yrBV5l7TgJCpLjaePHRj8joNlPmX9ukaRbTKCgCwuxk=; b=L39j2R+5Zk0bY46kVG4QPz4kIx42+g5nOVvcjCf1sYLOZw5CYC2Vm5V1EkBX+3mJla NUnZol4jFIcmHmJwpA5EqmBydVgYInlFyAsyvK+XTgeoXkjPw0IOQIL5e2AU7nDlabGQ u//+4BUlN9iLoxL1lnWsn1XWK5614pnECe9dto+cTNViQXlUVqb67sqf4ZigXh+rX6RM dWii64My3SjpsWAWadPaARPMsqCR8Uh5HByIArtFJV14+dTaAsBtohbMSxbwXzhwJ4ya kw8YBRzbfR96WhJI2piuZXY8b3NzgtGwGSXgY1xayK6CN9lyUwL262rHOJdXDTeET5fG WOLg== X-Gm-Message-State: AODbwcA4WwxuWcqlcosLK5QMW/DaMVx3ciApLfOc/HWTaYps2lsXijhb M+WJ2+B5Ki6rIcKzTdZwc/3FhQ4kSA== X-Received: by 10.157.28.135 with SMTP id l7mr72067ota.87.1496303318106; Thu, 01 Jun 2017 00:48:38 -0700 (PDT) MIME-Version: 1.0 Received: by 10.157.51.83 with HTTP; Thu, 1 Jun 2017 00:48:37 -0700 (PDT) In-Reply-To: <1496260914.15163.203.camel@brimstone.rchland.ibm.com> References: <1496260914.15163.203.camel@brimstone.rchland.ibm.com> From: Richard Biener Date: Thu, 01 Jun 2017 07:49:00 -0000 Message-ID: Subject: Re: [PATCH, rs6000] Fold vector shifts in GIMPLE To: will_schmidt@vnet.ibm.com, Jakub Jelinek Cc: GCC Patches , Segher Boessenkool , David Edelsohn , Bill Schmidt Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2017-06/txt/msg00005.txt.bz2 On Wed, May 31, 2017 at 10:01 PM, Will Schmidt wrote: > Hi, > > Add support for early expansion of vector shifts. Including > vec_sl (shift left), vec_sr (shift right), vec_sra (shift > right algebraic), vec_rl (rotate left). > Part of this includes adding the vector shift right instructions to > the list of those instructions having an unsigned second argument. > > The VSR (vector shift right) folding is a bit more complex than > the others. This is due to requiring arg0 be unsigned for an algebraic > shift before the gimple RSHIFT_EXPR assignment is built. Jakub, do we sanitize that undefinedness of left shifts of negative values and/or overflow of left shift of nonnegative values? Will, how is that defined in the intrinsics operation? It might need similar treatment as the abs case. [I'd rather make the negative left shift case implementation defined given C and C++ standards do not agree to 100% AFAIK] Richard. > [gcc] > > 2017-05-26 Will Schmidt > > * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling > for early expansion of vector shifts (sl,sr,sra,rl). > (builtin_function_type): Add vector shift right instructions > to the unsigned argument list. > > [gcc/testsuite] > > 2017-05-26 Will Schmidt > > * testsuite/gcc.target/powerpc/fold-vec-shift-char.c: New. > * testsuite/gcc.target/powerpc/fold-vec-shift-int.c: New. > * testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c: New. > * testsuite/gcc.target/powerpc/fold-vec-shift-short.c: New. > > diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c > index 8adbc06..6ee0bfd 100644 > --- a/gcc/config/rs6000/rs6000.c > +++ b/gcc/config/rs6000/rs6000.c > @@ -17408,6 +17408,76 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) > gsi_replace (gsi, g, true); > return true; > } > + /* Flavors of vec_rotate_left . */ > + case ALTIVEC_BUILTIN_VRLB: > + case ALTIVEC_BUILTIN_VRLH: > + case ALTIVEC_BUILTIN_VRLW: > + case P8V_BUILTIN_VRLD: > + { > + arg0 = gimple_call_arg (stmt, 0); > + arg1 = gimple_call_arg (stmt, 1); > + lhs = gimple_call_lhs (stmt); > + gimple *g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1); > + gimple_set_location (g, gimple_location (stmt)); > + gsi_replace (gsi, g, true); > + return true; > + } > + /* Flavors of vector shift right algebraic. vec_sra{b,h,w} -> vsra{b,h,w}. */ > + case ALTIVEC_BUILTIN_VSRAB: > + case ALTIVEC_BUILTIN_VSRAH: > + case ALTIVEC_BUILTIN_VSRAW: > + case P8V_BUILTIN_VSRAD: > + { > + arg0 = gimple_call_arg (stmt, 0); > + arg1 = gimple_call_arg (stmt, 1); > + lhs = gimple_call_lhs (stmt); > + gimple *g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1); > + gimple_set_location (g, gimple_location (stmt)); > + gsi_replace (gsi, g, true); > + return true; > + } > + /* Flavors of vector shift left. builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */ > + case ALTIVEC_BUILTIN_VSLB: > + case ALTIVEC_BUILTIN_VSLH: > + case ALTIVEC_BUILTIN_VSLW: > + case P8V_BUILTIN_VSLD: > + { > + arg0 = gimple_call_arg (stmt, 0); > + arg1 = gimple_call_arg (stmt, 1); > + lhs = gimple_call_lhs (stmt); > + gimple *g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, arg1); > + gimple_set_location (g, gimple_location (stmt)); > + gsi_replace (gsi, g, true); > + return true; > + } > + /* Flavors of vector shift right. */ > + case ALTIVEC_BUILTIN_VSRB: > + case ALTIVEC_BUILTIN_VSRH: > + case ALTIVEC_BUILTIN_VSRW: > + case P8V_BUILTIN_VSRD: > + { > + arg0 = gimple_call_arg (stmt, 0); > + arg1 = gimple_call_arg (stmt, 1); > + lhs = gimple_call_lhs (stmt); > + gimple *g; > + /* convert arg0 to unsigned */ > + arg0 = convert(unsigned_type_for(TREE_TYPE(arg0)),arg0); > + tree arg0_uns = create_tmp_reg_or_ssa_name(unsigned_type_for(TREE_TYPE(arg0))); > + g = gimple_build_assign(arg0_uns,arg0); > + gimple_set_location (g, gimple_location (stmt)); > + gsi_insert_before (gsi, g, GSI_SAME_STMT); > + /* convert lhs to unsigned and do the shift. */ > + tree lhs_uns = create_tmp_reg_or_ssa_name(unsigned_type_for(TREE_TYPE(lhs))); > + g = gimple_build_assign (lhs_uns, RSHIFT_EXPR, arg0_uns, arg1); > + gimple_set_location (g, gimple_location (stmt)); > + gsi_insert_before (gsi, g, GSI_SAME_STMT); > + /* convert lhs back to a signed type for the return. */ > + lhs_uns = convert(signed_type_for(TREE_TYPE(lhs)),lhs_uns); > + g = gimple_build_assign(lhs,lhs_uns); > + gimple_set_location (g, gimple_location (stmt)); > + gsi_replace (gsi, g, true); > + return true; > + } > default: > break; > } > @@ -19128,6 +19198,14 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, > h.uns_p[2] = 1; > break; > > + /* unsigned second arguments (vector shift right). */ > + case ALTIVEC_BUILTIN_VSRB: > + case ALTIVEC_BUILTIN_VSRH: > + case ALTIVEC_BUILTIN_VSRW: > + case P8V_BUILTIN_VSRD: > + h.uns_p[2] = 1; > + break; > + > default: > break; > } > diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-char.c > new file mode 100644 > index 0000000..ebe91e7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-char.c > @@ -0,0 +1,66 @@ > +/* Verify that overloaded built-ins for vec_sl with char > + inputs produce the right results. */ > + > +/* { dg-do compile } */ > +/* { dg-require-effective-target powerpc_altivec_ok } */ > +/* { dg-options "-maltivec -O2" } */ > + > +#include > + > +//# vec_sl - shift left > +//# vec_sr - shift right > +//# vec_sra - shift right algebraic > +//# vec_rl - rotate left > + > +vector signed char > +testsl_signed (vector signed char x, vector unsigned char y) > +{ > + return vec_sl (x, y); > +} > + > +vector unsigned char > +testsl_unsigned (vector unsigned char x, vector unsigned char y) > +{ > + return vec_sl (x, y); > +} > + > +vector signed char > +testsr_signed (vector signed char x, vector unsigned char y) > +{ > + return vec_sr (x, y); > +} > + > +vector unsigned char > +testsr_unsigned (vector unsigned char x, vector unsigned char y) > +{ > + return vec_sr (x, y); > +} > + > +vector signed char > +testsra_signed (vector signed char x, vector unsigned char y) > +{ > + return vec_sra (x, y); > +} > + > +vector unsigned char > +testsra_unsigned (vector unsigned char x, vector unsigned char y) > +{ > + return vec_sra (x, y); > +} > + > +vector signed char > +testrl_signed (vector signed char x, vector unsigned char y) > +{ > + return vec_rl (x, y); > +} > + > +vector unsigned char > +testrl_unsigned (vector unsigned char x, vector unsigned char y) > +{ > + return vec_rl (x, y); > +} > + > +/* { dg-final { scan-assembler-times "vslb" 2 } } */ > +/* { dg-final { scan-assembler-times "vsrb" 2 } } */ > +/* { dg-final { scan-assembler-times "vsrab" 2 } } */ > +/* { dg-final { scan-assembler-times "vrlb" 2 } } */ > diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-int.c > new file mode 100644 > index 0000000..e9c5fe1 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-int.c > @@ -0,0 +1,61 @@ > +/* Verify that overloaded built-ins for vec_sl with int > + inputs produce the right results. */ > + > +/* { dg-do compile } */ > +/* { dg-require-effective-target powerpc_altivec_ok } */ > +/* { dg-options "-maltivec -O2" } */ > + > +#include > + > +vector signed int > +testsl_signed (vector signed int x, vector unsigned int y) > +{ > + return vec_sl (x, y); > +} > + > +vector unsigned int > +testsl_unsigned (vector unsigned int x, vector unsigned int y) > +{ > + return vec_sl (x, y); > +} > + > +vector signed int > +testsr_signed (vector signed int x, vector unsigned int y) > +{ > + return vec_sr (x, y); > +} > + > +vector unsigned int > +testsr_unsigned (vector unsigned int x, vector unsigned int y) > +{ > + return vec_sr (x, y); > +} > + > +vector signed int > +testsra_signed (vector signed int x, vector unsigned int y) > +{ > + return vec_sra (x, y); > +} > + > +vector unsigned int > +testsra_unsigned (vector unsigned int x, vector unsigned int y) > +{ > + return vec_sra (x, y); > +} > + > +vector signed int > +testrl_signed (vector signed int x, vector unsigned int y) > +{ > + return vec_rl (x, y); > +} > + > +vector unsigned int > +testrl_unsigned (vector unsigned int x, vector unsigned int y) > +{ > + return vec_rl (x, y); > +} > + > +/* { dg-final { scan-assembler-times "vslw" 2 } } */ > +/* { dg-final { scan-assembler-times "vsrw" 2 } } */ > +/* { dg-final { scan-assembler-times "vsraw" 2 } } */ > +/* { dg-final { scan-assembler-times "vrlw" 2 } } */ > diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c > new file mode 100644 > index 0000000..97b82cf > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c > @@ -0,0 +1,63 @@ > +/* Verify that overloaded built-ins for vec_sl with long long > + inputs produce the right results. */ > + > +/* { dg-do compile } */ > +/* { dg-require-effective-target powerpc_p8vector_ok } */ > +/* { dg-options "-mpower8-vector -O2" } */ > + > +#include > + > +vector signed long long > +testsl_signed (vector signed long long x, vector unsigned long long y) > +{ > + return vec_sl (x, y); > +} > + > +vector unsigned long long > +testsl_unsigned (vector unsigned long long x, vector unsigned long long y) > +{ > + return vec_sl (x, y); > +} > + > +vector signed long long > +testsr_signed (vector signed long long x, vector unsigned long long y) > +{ > + return vec_sr (x, y); > +} > + > +vector unsigned long long > +testsr_unsigned (vector unsigned long long x, vector unsigned long long y) > +{ > + return vec_sr (x, y); > +} > + > +vector signed long long > +testsra_signed (vector signed long long x, vector unsigned long long y) > +{ > + return vec_sra (x, y); > +} > + > +/* watch for PR 79544 here (vsrd / vsrad issue) */ > +vector unsigned long long > +testsra_unsigned (vector unsigned long long x, vector unsigned long long y) > +{ > + return vec_sra (x, y); > +} > + > +vector signed long long > +testrl_signed (vector signed long long x, vector unsigned long long y) > +{ > + return vec_rl (x, y); > +} > + > +vector unsigned long long > +testrl_unsigned (vector unsigned long long x, vector unsigned long long y) > +{ > + return vec_rl (x, y); > +} > + > +/* { dg-final { scan-assembler-times "vsld" 2 } } */ > +/* { dg-final { scan-assembler-times "vsrd" 2 } } */ > +/* { dg-final { scan-assembler-times "vsrad" 2 } } */ > +/* { dg-final { scan-assembler-times "vrld" 2 } } */ > + > diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-short.c > new file mode 100644 > index 0000000..4ca7c18 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-short.c > @@ -0,0 +1,61 @@ > +/* Verify that overloaded built-ins for vec_sl with short > + inputs produce the right results. */ > + > +/* { dg-do compile } */ > +/* { dg-require-effective-target powerpc_altivec_ok } */ > +/* { dg-options "-maltivec -O2" } */ > + > +#include > + > +vector signed short > +testsl_signed (vector signed short x, vector unsigned short y) > +{ > + return vec_sl (x, y); > +} > + > +vector unsigned short > +testsl_unsigned (vector unsigned short x, vector unsigned short y) > +{ > + return vec_sl (x, y); > +} > + > +vector signed short > +testsr_signed (vector signed short x, vector unsigned short y) > +{ > + return vec_sr (x, y); > +} > + > +vector unsigned short > +testsr_unsigned (vector unsigned short x, vector unsigned short y) > +{ > + return vec_sr (x, y); > +} > + > +vector signed short > +testsra_signed (vector signed short x, vector unsigned short y) > +{ > + return vec_sra (x, y); > +} > + > +vector unsigned short > +testsra_unsigned (vector unsigned short x, vector unsigned short y) > +{ > + return vec_sra (x, y); > +} > + > +vector signed short > +testrl_signed (vector signed short x, vector unsigned short y) > +{ > + return vec_rl (x, y); > +} > + > +vector unsigned short > +testrl_unsigned (vector unsigned short x, vector unsigned short y) > +{ > + return vec_rl (x, y); > +} > + > +/* { dg-final { scan-assembler-times "vslh" 2 } } */ > +/* { dg-final { scan-assembler-times "vsrh" 2 } } */ > +/* { dg-final { scan-assembler-times "vsrah" 2 } } */ > +/* { dg-final { scan-assembler-times "vrlh" 2 } } */ > > >