From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by sourceware.org (Postfix) with ESMTPS id 888953858D38 for ; Thu, 17 Aug 2023 08:45:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 888953858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2b9aa1d3029so115480281fa.2 for ; Thu, 17 Aug 2023 01:45:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1692261944; x=1692866744; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=6praCbd3gT5u8SZKiUosO1vmXo/a05Zt7gQ559fQllA=; b=oowb/6uaAElB8wnlZfsghuJQxx4VD7IlA6vyWvumtFj8wncqpjDIB8hV+77a3KqKi0 Igs74UbM3FA3I0q1oah34sDmGYBH3KeYt8k+6JojAZ5Xp8yS4b7f8YiwR2/TP/ksKP99 2rQec3QH9pki5o/u/3ZRZApMUCjrHY9PuhizBxcSrKeo8t8N4rUI/uqL/JUbvJIy6Ym2 rfEx6NM/Ub2TKJjmYc09aVANKZDhii62UDsIJbHOggehiduGbGTMV14lg6mKSdlK+xQ3 uHRXa66Pp4nuFsYH6Xe6LEgjj6Q65MahyPxlMIFoCPjCRTQxStNqmqqi0gMAjEnpppFL f94w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692261944; x=1692866744; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6praCbd3gT5u8SZKiUosO1vmXo/a05Zt7gQ559fQllA=; b=HIcLDyK8A/1Sfam8yak02rS4uwmtRicaDeB4aY3dLZjOfrEfH/thc96Jgg2XM0vUNa BJR7jYpFUvk+mCUEv8+8bppfAgtzI+ocSm/W3bjls62krrdVW9oxnPD+qmFOpIgPtz86 6iXb9+4aDoQFE8aWG6OwXlnb+ntGmfenIny3Q2X7atYTS55xHG43ovdNbbOWr+DTGUNo hMX6uy44xspAiwqb7A5rkW/V8OnDPTD8jQIbCd4wPwBgd7M3yH8X6shhnbcXCucwL3mw hYX+jFrsGQEBw7GjqHoGOuFsiDFXa2Tn4j/ztgim0cqBFm/tMoVfMMmXG2nLBzqmAaMC IBSw== X-Gm-Message-State: AOJu0Yxlr+Ikr4hOlmzwqntitd6V5KVyJbBgXPNYXkAV/9ug5DkXM+Jc mW6JfjYI8pPQqI9AMCtKpNFNZa8EJqVlDaglJ9Z9PZwF X-Google-Smtp-Source: AGHT+IGrSL1leArdsAmrVx/TDpN1z8Ew24MLtmQ0byhHV22oIyQzUagPxsqBHLi7NJek2acsXqsWeLD/Qqsi3nGDpTs= X-Received: by 2002:a2e:7207:0:b0:2b6:f1d5:619 with SMTP id n7-20020a2e7207000000b002b6f1d50619mr3430984ljc.14.1692261943798; Thu, 17 Aug 2023 01:45:43 -0700 (PDT) MIME-Version: 1.0 References: <20230815184618.7396-1-david.faust@oracle.com> <87cyzo3z8c.fsf@oracle.com> In-Reply-To: <87cyzo3z8c.fsf@oracle.com> From: Richard Biener Date: Thu, 17 Aug 2023 10:44:23 +0200 Message-ID: Subject: Re: [PATCH] bpf: fix pseudoc w regs for small modes [PR111029] To: "Jose E. Marchesi" Cc: David Faust , gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Aug 15, 2023 at 9:03=E2=80=AFPM Jose E. Marchesi via Gcc-patches wrote: > > > Hello David. > Thanks for the patch. > > OK. Picking a random patch/mail for this question - how do we maintain BPF support for the most recent GCC release which is GCC 13? I see the current state in GCC 13 isn't fully able to provide upstream kernel BPF support but GCC 14 contains some bugfixes and some new features(?). Is it worthwhile to backport at least bugfixes while GCC 14 is still in development even if those are not regression fixes? Or is GCC 13 BPF too broken to be used anyway? Thanks, Richard. > > In the BPF pseudo-c assembly dialect, registers treated as 32-bits > > rather than the full 64 in various instructions ought to be printed as > > "wN" rather than "rN". But bpf_print_register () was only doing this > > for specifically SImode registers, meaning smaller modes were printed > > incorrectly. > > > > This caused assembler errors like: > > > > Error: unrecognized instruction `w2 =3D(s8)r1' > > > > for a 32-bit sign-extending register move instruction, where the source > > register is used in QImode. > > > > Fix bpf_print_register () to print the "w" version of register when > > specified by the template for any mode 32-bits or smaller. > > > > Tested on bpf-unknown-none. > > > > PR target/111029 > > > > gcc/ > > * config/bpf/bpf.cc (bpf_print_register): Print 'w' registers > > for any mode 32-bits or smaller, not just SImode. > > > > gcc/testsuite/ > > > > * gcc.target/bpf/smov-2.c: New test. > > * gcc.target/bpf/smov-pseudoc-2.c: New test. > > --- > > gcc/config/bpf/bpf.cc | 2 +- > > gcc/testsuite/gcc.target/bpf/smov-2.c | 15 +++++++++++++++ > > gcc/testsuite/gcc.target/bpf/smov-pseudoc-2.c | 15 +++++++++++++++ > > 3 files changed, 31 insertions(+), 1 deletion(-) > > create mode 100644 gcc/testsuite/gcc.target/bpf/smov-2.c > > create mode 100644 gcc/testsuite/gcc.target/bpf/smov-pseudoc-2.c > > > > diff --git a/gcc/config/bpf/bpf.cc b/gcc/config/bpf/bpf.cc > > index 3516b79bce4..1d0abd7fbb3 100644 > > --- a/gcc/config/bpf/bpf.cc > > +++ b/gcc/config/bpf/bpf.cc > > @@ -753,7 +753,7 @@ bpf_print_register (FILE *file, rtx op, int code) > > fprintf (file, "%s", reg_names[REGNO (op)]); > > else > > { > > - if (code =3D=3D 'w' && GET_MODE (op) =3D=3D SImode) > > + if (code =3D=3D 'w' && GET_MODE_SIZE (GET_MODE (op)) <=3D 4) > > { > > if (REGNO (op) =3D=3D BPF_FP) > > fprintf (file, "w10"); > > diff --git a/gcc/testsuite/gcc.target/bpf/smov-2.c b/gcc/testsuite/gcc.= target/bpf/smov-2.c > > new file mode 100644 > > index 00000000000..6f3516d2385 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/bpf/smov-2.c > > @@ -0,0 +1,15 @@ > > +/* Check signed 32-bit mov instructions. */ > > +/* { dg-do compile } */ > > +/* { dg-options "-mcpu=3Dv4 -O2" } */ > > + > > +int > > +foo (unsigned char a, unsigned short b) > > +{ > > + int x =3D (char) a; > > + int y =3D (short) b; > > + > > + return x + y; > > +} > > + > > +/* { dg-final { scan-assembler {movs32\t%r.,%r.,8\n} } } */ > > +/* { dg-final { scan-assembler {movs32\t%r.,%r.,16\n} } } */ > > diff --git a/gcc/testsuite/gcc.target/bpf/smov-pseudoc-2.c b/gcc/testsu= ite/gcc.target/bpf/smov-pseudoc-2.c > > new file mode 100644 > > index 00000000000..6af6cadf8df > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/bpf/smov-pseudoc-2.c > > @@ -0,0 +1,15 @@ > > +/* Check signed 32-bit mov instructions (pseudo-C asm dialect). */ > > +/* { dg-do compile } */ > > +/* { dg-options "-mcpu=3Dv4 -O2 -masm=3Dpseudoc" } */ > > + > > +int > > +foo (unsigned char a, unsigned short b) > > +{ > > + int x =3D (char) a; > > + int y =3D (short) b; > > + > > + return x + y; > > +} > > + > > +/* { dg-final { scan-assembler {w. =3D \(s8\) w.\n} } } */ > > +/* { dg-final { scan-assembler {w. =3D \(s16\) w.\n} } } */