From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by sourceware.org (Postfix) with ESMTPS id 28D863858D1E for ; Tue, 8 Nov 2022 15:04:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 28D863858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x636.google.com with SMTP id y14so39348424ejd.9 for ; Tue, 08 Nov 2022 07:04:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=PeV4sDGGd/63PCseG4BO5qcUih/RKS+7X/gGHlmPnec=; b=lHDjzSc4ckZB61QU/Iyu7uCb0SpsPnh40EOS3U3CeqNNGiwXkEULW0THUwuHf3KnS9 Cb+IlGHHDGDc/eMSmduszh/rn+gPAXIg1WeDikycZVj/TovdvShOs6+6Ye9QNtA30peP wa1JMEVPzEo1gaUnfayMQMkSQnFDNDea6zbeQFoKUTNU5m05t5Okt08W2SXKtkTkP+tx VWK+O/PNOdovVK0/rNSV/cOOSfjw56A+Ot7dgrwrKLNUk2yH5e37Dp7o45iyu4GZ/A5I v9EE8IAYFNxBaH3qdslU1b8miRsGArXNj74PapmenZ5LDFx1WkRqVnDLj7mcZfGQ5Bcc NkBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=PeV4sDGGd/63PCseG4BO5qcUih/RKS+7X/gGHlmPnec=; b=SdEenQqKfgftvwvFCYdR0MpravzwWghMPZzixSTG4TvUteUiO+gY6MGNx4EqRTYq1Y J+BtkwWKYtdMEKVYL7TwpnbYNfDe9UTK7m6lnMEOYrz8nzl7BKEcJdZ2u6lv74kL+4E2 yE/Qu0IQxkmS+8BXlY6GHB6a/T0/iLd3aO2SbzBnljSHkYn0GRMTx7oRywubJ2qTYiOf NYquLZ786Fnb6WQSvrUgPemqBZ+eso8DlFbqy4xE6SgEsf2prTWalz/AZm3f7nhYp9xN SetxeC6u4hI+AZ0IYXPzof2USbfbVPgCZuQiwTUAIlatVCH9LZzM0yyO2aEVkwdWfBUa Wq4Q== X-Gm-Message-State: ANoB5plnFnpAEPgeKPL2Brqf9XAZ9uyBVM8D3tFrrrRKqt9NHQTHAcQk IbLnrsWJ1O+feKuHnf32iMHtUunNCveIRfeohC3/1NEK X-Google-Smtp-Source: AA0mqf78aI2bz4IM+vkDxQB5yWNi+8fBGg2B6Vxn/aJ1oH7wjt1Rig3R/ZgTgBd+jctcB5NDh5P6/rnwr8krKdutMxw= X-Received: by 2002:a17:907:778a:b0:7ae:743c:61c1 with SMTP id ky10-20020a170907778a00b007ae743c61c1mr6913491ejc.511.1667919878878; Tue, 08 Nov 2022 07:04:38 -0800 (PST) MIME-Version: 1.0 References: <20221108142458.862678-1-aldyh@redhat.com> In-Reply-To: <20221108142458.862678-1-aldyh@redhat.com> From: Richard Biener Date: Tue, 8 Nov 2022 16:04:26 +0100 Message-ID: Subject: Re: [PATCH] CCP: handle division by a power of 2 as a right shift. To: Aldy Hernandez Cc: GCC patches , Andrew MacLeod Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Nov 8, 2022 at 3:25 PM Aldy Hernandez wrote: > > We have some code in range-ops that sets better maybe nonzero bits for > TRUNC_DIV_EXPR by a power of 2 than CCP does, by just shifting the > mask. I'd like to offload this functionality into the CCP mask > tracking code, which already does the right thing for right shifts. > > The testcase for this change is gcc.dg/tree-ssa/vrp123.c and > gcc.dg/tree-ssa/pr107541.c. > > Tested on x86-64 Linux. > > OK? LGTM > gcc/ChangeLog: > > * range-op.cc (operator_div::fold_range): Call > update_known_bitmask. > * tree-ssa-ccp.cc (bit_value_binop): Handle divisions by powers of > 2 as a right shift. > --- > gcc/range-op.cc | 18 +----------------- > gcc/tree-ssa-ccp.cc | 12 ++++++++++++ > 2 files changed, 13 insertions(+), 17 deletions(-) > > diff --git a/gcc/range-op.cc b/gcc/range-op.cc > index 846931ddcae..8ff5d5b4c78 100644 > --- a/gcc/range-op.cc > +++ b/gcc/range-op.cc > @@ -1995,23 +1995,7 @@ operator_div::fold_range (irange &r, tree type, > if (!cross_product_operator::fold_range (r, type, lh, rh, trio)) > return false; > > - if (lh.undefined_p ()) > - return true; > - > - tree t; > - if (code == TRUNC_DIV_EXPR > - && rh.singleton_p (&t) > - && !wi::neg_p (lh.lower_bound ())) > - { > - wide_int wi = wi::to_wide (t); > - int shift = wi::exact_log2 (wi); > - if (shift != -1) > - { > - wide_int nz = lh.get_nonzero_bits (); > - nz = wi::rshift (nz, shift, TYPE_SIGN (type)); > - r.set_nonzero_bits (nz); > - } > - } > + update_known_bitmask (r, code, lh, rh); > return true; > } > > diff --git a/gcc/tree-ssa-ccp.cc b/gcc/tree-ssa-ccp.cc > index 3a4b6bc1118..2bcd90646f6 100644 > --- a/gcc/tree-ssa-ccp.cc > +++ b/gcc/tree-ssa-ccp.cc > @@ -1934,6 +1934,18 @@ bit_value_binop (enum tree_code code, signop sgn, int width, > { > widest_int r1max = r1val | r1mask; > widest_int r2max = r2val | r2mask; > + if (r2mask == 0 && !wi::neg_p (r1max)) > + { > + widest_int shift = wi::exact_log2 (r2val); > + if (shift != -1) > + { > + // Handle division by a power of 2 as an rshift. > + bit_value_binop (RSHIFT_EXPR, sgn, width, val, mask, > + r1type_sgn, r1type_precision, r1val, r1mask, > + r2type_sgn, r2type_precision, shift, r2mask); > + return; > + } > + } > if (sgn == UNSIGNED > || (!wi::neg_p (r1max) && !wi::neg_p (r2max))) > { > -- > 2.38.1 >