From: Richard Biener <richard.guenther@gmail.com>
To: Jiong Wang <jiong.wang@arm.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH] PR 62173, re-shuffle insns for RTL loop invariant hoisting
Date: Thu, 04 Dec 2014 11:07:00 -0000 [thread overview]
Message-ID: <CAFiYyc1jauY_hejCfgU88DXtaSCCSZDUMiKMb678KqQ_QrMzrQ@mail.gmail.com> (raw)
In-Reply-To: <54803EBE.2060607@arm.com>
On Thu, Dec 4, 2014 at 12:00 PM, Jiong Wang <jiong.wang@arm.com> wrote:
> For PR62173, the ideal solution is to resolve the problem on tree level
> ivopt pass.
>
> While, apart from the tree level issue, PR 62173 also exposed another two
> RTL level issues.
> one of them is looks like we could improve RTL level loop invariant hoisting
> by re-shuffle insns.
>
> for Seb's testcase
>
> void bar(int i) {
> char A[10];
> int d = 0;
> while (i > 0)
> A[d++] = i--;
>
> while (d > 0)
> foo(A[d--]);
> }
>
> the insn sequences to calculate A[I]'s address looks like:
>
> (insn 76 75 77 22 (set (reg/f:DI 109)
> (plus:DI (reg/f:DI 64 sfp)
> (reg:DI 108 [ i ]))) seb-pop.c:8 84 {*adddi3_aarch64}
> (expr_list:REG_DEAD (reg:DI 108 [ i ])
> (nil)))
> (insn 77 76 78 22 (set (reg:SI 110 [ D.2633 ])
> (zero_extend:SI (mem/j:QI (plus:DI (reg/f:DI 109)
> (const_int -16 [0xfffffffffffffff0])) [0 A S1 A8]))) seb-pop.c:8 76
> {*zero_extendqisi2_aarch64}
> (expr_list:REG_DEAD (reg/f:DI 109)
> (nil)))
>
> while for most RISC archs, reg + reg addressing is typical, so if we
> re-shuffle
> the instruction sequences into the following:
>
> (insn 96 94 97 22 (set (reg/f:DI 129)
> (plus:DI (reg/f:DI 64 sfp)
> (const_int -16 [0xfffffffffffffff0]))) seb-pop.c:8 84 {*adddi3_aarch64}
> (nil))
> (insn 97 96 98 22 (set (reg:DI 130 [ i ])
> (sign_extend:DI (reg/v:SI 97 [ i ]))) seb-pop.c:8 70
> {*extendsidi2_aarch64}
> (expr_list:REG_DEAD (reg/v:SI 97 [ i ])
> (nil)))
> (insn 98 97 99 22 (set (reg:SI 131 [ D.2633 ])
> (zero_extend:SI (mem/j:QI (plus:DI (reg/f:DI 129)
> (reg:DI 130 [ i ])) [0 A S1 A8]))) seb-pop.c:8 76
> {*zero_extendqisi2_aarch64}
> (expr_list:REG_DEAD (reg:DI 130 [ i ])
> (expr_list:REG_DEAD (reg/f:DI 129)
> (nil))))
>
> which means re-associate the constant imm with the virtual frame pointer.
>
> transform
>
> RA <- fixed_reg + RC
> RD <- MEM (RA + const_offset)
>
> into:
>
> RA <- fixed_reg + const_offset
> RD <- MEM (RA + RC)
>
> then RA <- fixed_reg + const_offset is actually loop invariant, so the later
> RTL GCSE PRE pass could catch it and do the hoisting, and thus ameliorate
> what tree
> level ivopts could not sort out.
There is a LIM pass after gimple ivopts - if the invariantness is already
visible there why not handle it there similar to the special-cases in
rewrite_bittest and rewrite_reciprocal?
And of course similar tricks could be applied on the RTL level to
RTL invariant motion?
Thanks,
Richard.
> and this patch only tries to re-shuffle instructions within single basic
> block which
> is a inner loop which is perf critical.
>
> I am reusing the loop info in fwprop because there is loop info and it's run
> before
> GCSE.
>
> verified on aarch64 and mips64, the array base address hoisted out of loop.
>
> bootstrap ok on x86-64 and aarch64.
>
> comments?
>
> thanks.
>
> gcc/
> PR62173
> fwprop.c (prepare_for_gcse_pre): New function.
> (fwprop_done): Call it.
next prev parent reply other threads:[~2014-12-04 11:07 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-04 11:00 Jiong Wang
2014-12-04 11:07 ` Richard Biener [this message]
2014-12-04 11:07 ` Richard Biener
2014-12-04 19:32 ` Jiong Wang
2014-12-15 15:29 ` Jiong Wang
2014-12-15 15:36 ` Jiong Wang
2014-12-17 16:19 ` Richard Biener
2014-12-18 17:08 ` Jiong Wang
2014-12-18 21:16 ` Jiong Wang
2014-12-18 22:19 ` Segher Boessenkool
2014-12-19 4:06 ` Bin.Cheng
2014-12-19 10:29 ` Jiong Wang
2014-12-19 11:45 ` Richard Biener
2014-12-19 15:31 ` Kenneth Zadeck
2015-02-11 11:20 ` Jiong Wang
2015-02-11 14:22 ` Kenneth Zadeck
2015-02-11 18:18 ` Jiong Wang
2015-04-14 15:06 ` Jiong Wang
2015-04-14 16:49 ` Steven Bosscher
2015-04-14 17:24 ` Jeff Law
2015-04-14 21:49 ` Jiong Wang
2015-04-21 14:43 ` Jiong Wang
2015-04-24 1:55 ` Jeff Law
2015-04-24 17:05 ` Jiong Wang
2015-05-14 20:04 ` Jeff Law
2015-05-14 22:07 ` Jiong Wang
2015-05-14 22:24 ` Jeff Law
2015-05-21 21:51 ` Jiong Wang
2015-05-27 16:11 ` Jeff Law
2015-09-02 13:49 ` Jiong Wang
2015-09-02 20:52 ` Jeff Law
2015-04-28 12:16 ` Jiong Wang
2015-04-28 14:00 ` Matthew Fortune
2015-04-28 14:31 ` Jiong Wang
2015-04-19 16:20 ` Jiong Wang
2014-12-19 12:09 ` Eric Botcazou
2014-12-19 15:21 ` Segher Boessenkool
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAFiYyc1jauY_hejCfgU88DXtaSCCSZDUMiKMb678KqQ_QrMzrQ@mail.gmail.com \
--to=richard.guenther@gmail.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=jiong.wang@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).