From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by sourceware.org (Postfix) with ESMTPS id 67B643858C5F for ; Tue, 14 Nov 2023 12:52:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 67B643858C5F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 67B643858C5F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::12d ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699966330; cv=none; b=Z5h/OOTevqQyLqTLliRl3L0o7+iE/0LVL2qkq3xiKE0YUFDaBZKqKE2h0xfGEYRSyA0sK6yRqHKsDd3OSJW9XO3rs5IodTnxXSYXxVNvPkWf+Gp4QRHMNGIcTm9MJbwgnQZ5H4K5TOcrk6BzoQu4uZ7+AljgDqYLJhFKjr4vEiY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699966330; c=relaxed/simple; bh=+oX/t6aQEAL5NVuN1VrVS/flnSFjl4DdAmO4xkYQtbM=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=ZaneBo3bdkaKD8ipvhaiQl0OzA+Do1KS+9O2dgz2bx6lZcasEjCOsCmqWdKFwmfQWHoGK53J9FY174ISZOyKlLhmOWc9jV5r8I6mwwtyhtjN3KyJ41+mexzEJwkYvakOm4SEMVhMJsv2UoIOnsyqweYO5pzE641CLRpUnclS0dE= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-50a6ff9881fso6693763e87.1 for ; Tue, 14 Nov 2023 04:52:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1699966327; x=1700571127; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=yInsvBZ5c49sd1JnrivTPd0qZ/tl9sY1qExcubj9VuM=; b=BqNzAoeoeV7X8y0U1bitMTlEqg7ZOOWuhm1GlqNTbxeFMyLSmaulsLA/J6ixeV/OlB csydMISvxFRHa8LxXZh5QxQoe4J0il9O4bL5lKD9ugVByTOV04pXVz2cnLRbhgr5VHpu wz0gQ68U1MlHLMc/wTUgGDqyVq//bsZvfzxYlRVC8axGGtHshm11eOtxrc2M43o5NRkx kxUuBSKBlk1oGJiL5cvI31ItOKsuuER0m2ofQ1mqaLe5uu8jqIvMvhsBNjKKm3NvzXlW txT170fvnSqvVib0+TO2a0Kkdf00DYwtVS/Rs2C4v3UT21B8rQwclNt/r1wDS6REDi4x pnsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699966327; x=1700571127; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yInsvBZ5c49sd1JnrivTPd0qZ/tl9sY1qExcubj9VuM=; b=f3EZFLcmutiNoL2xaUwn82Dvz4xpqPQMgDA7E0gvHCDQJvIS0RntE527TdeB84lZEK rw7LgEnzOshW75i9LkRgViejsfcAz9xHkeCUsyL4bEUYx7fwGSTv2PRP6yYSnba7LZ2i 6eCY4+xWD98rrBKd9XQqGNaAwz093A8m0q9g1kG4kdmmix5xPgKk2aF4YpLybiGduPrV gQMGqGHR9l2MGISHNadRxt8bt8mdySQGyipubxJMUJPKE/e8HsagCNdp7K/LZLF2OYVS W/w3NjNNRQ7S/PMgqSKHL7vf8AqV8eZgYXb/KcGIdLT87xpLHOXQeQkLrnfcoS4uD8/f uo6A== X-Gm-Message-State: AOJu0YzSmCGRW3ZPfmQY3XDs8TJ+BY3nlZSZCKWbIqQ8qvfrobOg2oNH 7FwGVEFNLYI9qduX+fuIInaR5E7lKkdpQgSkdXE= X-Google-Smtp-Source: AGHT+IGCoT/Sndm+XtxvX797Kk6LwnP3UEqp9P1qSojo4NVGtLt1Gx7EMQU/Wwq3dzDBOgAvt8euTD670JJoa/KVPyQ= X-Received: by 2002:ac2:5f72:0:b0:507:a6b6:d3c1 with SMTP id c18-20020ac25f72000000b00507a6b6d3c1mr6401745lfc.20.1699966326639; Tue, 14 Nov 2023 04:52:06 -0800 (PST) MIME-Version: 1.0 References: <00d701da15ab$b8971170$29c53450$@nextmovesoftware.com> In-Reply-To: From: Richard Biener Date: Tue, 14 Nov 2023 13:48:35 +0100 Message-ID: Subject: Re: [PATCH] i386: Fix up 3_doubleword_lowpart [PR112523] To: Jakub Jelinek Cc: Uros Bizjak , Roger Sayle , gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Nov 14, 2023 at 1:07=E2=80=AFPM Jakub Jelinek wr= ote: > > Hi! > > On Sun, Nov 12, 2023 at 09:03:42PM -0000, Roger Sayle wrote: > > This patch improves register pressure during reload, inspired by PR 977= 56. > > Normally, a double-word right-shift by a constant produces a double-wor= d > > result, the highpart of which is dead when followed by a truncation. > > The dead code calculating the high part gets cleaned up post-reload, so > > the issue isn't normally visible, except for the increased register > > pressure during reload, sometimes leading to odd register assignments. > > Providing a post-reload splitter, which clobbers a single wordmode > > result register instead of a doubleword result register, helps (a bit). > > Unfortunately this broke bootstrap on i686-linux, broke all ACATS tests > on x86_64-linux as well as miscompiled e.g. __floattisf in libgcc there > as well. > > The bug is that shrd{l,q} instruction expects the low part of the input > to be the same register as the output, rather than the high part as the > patch implemented. > split_double_mode (mode, &operands[1], 1, &operands[1], &operands[= 3]); > sets operands[1] to the lo_half and operands[3] to the hi_half, so if > operands[0] is not the same register as operands[1] (rather than [3]) aft= er > RA, we should during splitting move operands[1] into operands[0]. > > Your testcase: > > > #define MASK60 ((1ul << 60) - 1) > > unsigned long foo (__uint128_t n) > > { > > unsigned long a =3D n & MASK60; > > unsigned long b =3D (n >> 60); > > b =3D b & MASK60; > > unsigned long c =3D (n >> 120); > > return a+b+c; > > } > > still has the same number of instructions. > > Bootstrapped/regtested on x86_64-linux (where it e.g. turns > =3D=3D=3D acats Summary =3D=3D=3D > -# of unexpected failures 2328 > +# of expected passes 2328 > +# of unexpected failures 0 > and fixes gcc.dg/torture/fp-int-convert-*timode.c FAILs as well) > and i686-linux (where it previously didn't bootstrap, but compared to > Friday evening's bootstrap the testresults are ok), ok for trunk? OK. Thanks, Richard. > 2023-11-14 Jakub Jelinek > > PR target/112523 > PR ada/112514 > * config/i386/i386.md (3_doubleword_lowpart): Move > operands[1] aka low part of input rather than operands[3] aka hig= h > part of input to output if not the same register. > > --- gcc/config/i386/i386.md.jj 2023-11-14 08:10:18.932549803 +0100 > +++ gcc/config/i386/i386.md 2023-11-14 09:31:05.565019207 +0100 > @@ -14825,8 +14825,8 @@ (define_insn_and_split "3_dou > { > split_double_mode (mode, &operands[1], 1, &operands[1], &operands= [3]); > operands[4] =3D GEN_INT (( * BITS_PER_UNIT) - INTVAL (opera= nds[2])); > - if (!rtx_equal_p (operands[0], operands[3])) > - emit_move_insn (operands[0], operands[3]); > + if (!rtx_equal_p (operands[0], operands[1])) > + emit_move_insn (operands[0], operands[1]); > }) > > (define_insn "x86_64_shrd" > > > Jakub >