From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by sourceware.org (Postfix) with ESMTPS id 8D44C3858D33 for ; Tue, 21 Nov 2023 09:44:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8D44C3858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8D44C3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::130 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700559896; cv=none; b=gh1FTiN8UFs6bcE6b+8rfTwX0G1M+XbOJ98enAd+y+EcRM29W+MupNURkLHok2TJqXA8cJX2rtLn9vCCER+nuX2DbQY4Z/XNA1Nh/B3+JEe/SsDmQZEHTnGwUmfavehZ4UFPm17sWiCQ74PcRlXB1GztZZQrqLtnyftwEy+6+34= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700559896; c=relaxed/simple; bh=eqZm9Na5BQ5ekFJicp7nX8PC4FOi7NiDug4J5qNyUwc=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=rw0C6V84RNk4NMHpbGPuStKvR7NQ9qF7C7cE1ZobocnY/LVwVdqzzb93gspqU6mJo7X/s/S6/mkAC17A24qX5wmhn0Zv2QetLrxbNypviEAPhjv2WkJ2ut8mGcRD0QEVzXcpxWj2GsamTUHxZVx1I4QX/Q6bNUSkOpKXxsrep5I= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-507ad511315so7546427e87.0 for ; Tue, 21 Nov 2023 01:44:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700559893; x=1701164693; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=MFHxj0YG6xbI5jxDyOKIq6CH2xFWXpp51NMC3B48WlI=; b=ewIwmtHjgFUMTJLCcfJAheuzvi8XMgGc3Do/aoNYpnZRE8GaLVCdnAryCDxB5H/Jjp bKme8v8wN93OXkUxZ4CXYkBa8lRmB7TiiKZd4pbNeNVnBqr5lTIHDtwe1L84LNvezeLJ c/dIoXtK1b2gzkxuSM0LujBBULavvZTLwmktncUnfaUsnv2rGB15SZiSGLZux56luGqq c6EidjLgrwDYKcuHjUYE+9WNTVd+x/oUZsZDIjyZRHITgYAG9MaWTeVH0h7gqQ9XsrB1 GwYCAkRpKPWDm0QRZt22dTb3pIu+agtOTIKEi6scFwJVNfmQ8mNOYb6OYtN16H0q+zdj XP3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700559893; x=1701164693; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MFHxj0YG6xbI5jxDyOKIq6CH2xFWXpp51NMC3B48WlI=; b=l4Ow6bhl2KxdSceDrHaRciIev1tIhZkLVAfpOwEW8pz0bRgyjbHyc+H+UmBxnYe0lH 6iSZxSOZfrn9lxciVojWwQ23jKzG0Lpi5tVxFSPHDkIF3/UDvcM3GALdu8pLBBCVAdFT rzRMz8P8XHpEBsio1AYMyAUelN3RC7AVfTxGPaERHQN5tiegUrY/n3WWdfgDWqA/1ivR +faQnbiVsR2dcyY7PsM5arftjUSET7USMHj7EgTIe9G4azdqR2VwmG4uzypJv4PvOBiN jmxenW/FjqaOY3C4w+Hx2tGXa/gGP+WVKrhMw0X5I6Jds9jFpEqe4rn9ZMO0qZypG26B y1jA== X-Gm-Message-State: AOJu0YwLp/IQYNnbX8PJckG4DTugqOh2z+/pzYJzVoRsasjR9/qmEdkn W1NwR/SG06Si6SEOSl3WmLi1wVREI1n949Xuj/25JMuj X-Google-Smtp-Source: AGHT+IEPvEnSx0ZS4BrW8neWZ+q365RwWuaZMY+I4L+CD8Vq49l4T2UkR6nkAWjBLkbPIMmX35BpDBOR7isMq7tbRx0= X-Received: by 2002:ac2:51b5:0:b0:502:d743:9fc4 with SMTP id f21-20020ac251b5000000b00502d7439fc4mr7393609lfk.37.1700559892928; Tue, 21 Nov 2023 01:44:52 -0800 (PST) MIME-Version: 1.0 References: <6d44ca81-a0ec-4890-8537-2a4e403cb616@foss.arm.com> In-Reply-To: From: Richard Biener Date: Tue, 21 Nov 2023 10:41:13 +0100 Message-ID: Subject: Re: [PATCH]AArch64 docs: update -mcpu=generic definition on aarch64 To: Richard Earnshaw Cc: Tamar Christina , "gcc-patches@gcc.gnu.org" , nd , Richard Earnshaw , Marcus Shawcroft , Kyrylo Tkachov , Richard Sandiford Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Nov 21, 2023 at 10:38=E2=80=AFAM Richard Earnshaw wrote: > > > > On 20/11/2023 21:49, Tamar Christina wrote: > >> -----Original Message----- > >> From: Richard Earnshaw > >> Sent: Monday, November 20, 2023 12:53 PM > >> To: Tamar Christina ; gcc-patches@gcc.gnu.org > >> Cc: nd ; Richard Earnshaw ; > >> Marcus Shawcroft ; Kyrylo Tkachov > >> ; Richard Sandiford > >> > >> Subject: Re: [PATCH]AArch64 docs: update -mcpu=3Dgeneric definition on > >> aarch64 > >> > >> > >> > >> On 16/11/2023 15:19, Tamar Christina wrote: > >> > Hi All, > >> > > >> > This documents the behavior of the generic CPU options on AArch64. > >> > > >> > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > >> > > >> > Ok for master? > >> > > >> > Thanks, > >> > Tamar > >> > > >> > gcc/ChangeLog: > >> > > >> > * doc/invoke.texi (generic): Update defintion. > >> > (generic-armv8-a, generic-armv9-a): Document. > >> > > >> > --- inline copy of patch -- > >> > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index > >> > > >> d0b55fb106f908e8222394bbd07670aa583c5680..77684c5d7c9c0bdd5872 > >> 50acc190 > >> > da81e0f7f032 100644 > >> > --- a/gcc/doc/invoke.texi > >> > +++ b/gcc/doc/invoke.texi > >> > @@ -20759,7 +20759,8 @@ processors implementing the target > >> architecture. > >> > @item -mtune=3D@var{name} > >> > Specify the name of the target processor for which GCC should tune= the > >> > performance of the code. Permissible values for this option are: > >> > -@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, > >> > @samp{cortex-a55}, > >> > +@samp{generic}, @samp{generic-armv8-a}, @samp{generic-armv9-a}, > >> > +@samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, > >> > @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, > >> @samp{cortex-a75}, > >> > @samp{cortex-a76}, @samp{cortex-a76ae}, @samp{cortex-a77}, > >> > @samp{cortex-a65}, @samp{cortex-a65ae}, @samp{cortex-a34}, @@ > >> > -20798,6 +20799,11 @@ arithmetic instructions per cycle (2 for 256-b= it > >> SVE, 4 for 128-bit SVE). > >> > This is more general than tuning for a specific core like Neoverse= V1 > >> > but is more specific than the default tuning described below. > >> > > >> > +The value @samp{generic} should not be assumed to be a static > >> configuration. > >> > +Starting with GCC 14 this value can change over time in order to > >> > +better reflect advancements in CPU microarchitecture. If a specifi= c > >> > +version is required you are encouraged to use one of the architectu= re > >> specific generic processors, e.g. @samp{generic-armv8-a}. > >> > + > >> > Additionally on native AArch64 GNU/Linux systems the value > >> > @samp{native} tunes performance to the host system. This option h= as no > >> effect > >> > if the compiler is unable to recognize the processor of the host s= ystem. > >> > > >> > > >> > > >> > > >> @opindex mcpu > >> @item -mcpu=3D@var{name} > >> Specify the name of the target processor, optionally suffixed by one o= r more > >> feature modifiers. This option has the form @option{- > >> mcpu=3D@var{cpu}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the > >> permissible values for @var{cpu} are the same as those available > >> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > >> ^ > >> for @option{-mtune}. > >> ^^^^^^^^^^^^^^^^^^^^ > >> > >> So what is the behaviour now if these are used for -mcpu? Do we reall= y want > >> to permit their use here? > >> > > > > They behave as any other CPU but with the baseline architecture and no > > extensions > > i.e. -mcpu=3Dgeneric =3D=3D -march=3Darmv8-a -mtune=3Dgeneric. > > > > We've never blocked them before so doing so now would be a regression. > > Conceptually they do make sense as -mcpu values as they just mean "give= me > > the best compatibility with this architecture as a baseline". > > My point is that if 'generic' can change meaning from release to release > (which is acceptable for tune), then it becomes somewhat ambiguous (and > therefore useless) for a CPU. Which is why x86 doesn't have -march=3Dgeneric but only -mtune=3Dgeneric. IMHO options selecting ISA features shouldn't change their meaning over tim= e. > R.