From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by sourceware.org (Postfix) with ESMTPS id BF57E3853C02 for ; Mon, 2 Aug 2021 10:20:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BF57E3853C02 Received: by mail-ed1-x534.google.com with SMTP id b7so23766309edu.3 for ; Mon, 02 Aug 2021 03:20:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=lNNrBTHsQn2FffdRZbMC+QC2owcSt5QYwbF651F/g50=; b=qAay5QGBRguUJ3+Xcj05ORAwpoia3rCLq1BRg3FOYOkklgjClPWpwhgTfEevz+WB2B i5CfDfjLDzTDaw6AfSC2r2/FD3OY04qQEkxlw3tZ5J5XGJ9rYWDSFjizfgE/Mc3u4XhW dlmvc8j3gfz8pYmbXJyU6w4ccry5xnbNwBFVZMy2ibAgDBUnrxp0DSeEF6vtNtvw0fYG DhknN94L/mgpUN6Fg8HLNInrxyUkdP7oSAFMsALmVYa5NiQAMkEhYBEMkr5RQ5fTnyN+ 2CHO1f/ihO88KZij48ho6SjJNoK1fJvrUH7k8xq7QyJ3/nUppmIWbVfykSdSN9fJ8lwK HjVg== X-Gm-Message-State: AOAM532A9oCmhpBSrR7ggqkPovtaJP3AvoQYaFXj041/cfH8JdbBZGOD knJNP25G7uWzXABlP10Py64PIelfKcCOQGO8Af0= X-Google-Smtp-Source: ABdhPJxueUIv954nsWXRCB9UHCgGOX1FtoaENy4wGuNkax3IfDAHpU0VnjVHJn5cS9Jji0kW2U02bA2vICSe1jdbxhY= X-Received: by 2002:aa7:d9c3:: with SMTP id v3mr13132415eds.248.1627899600809; Mon, 02 Aug 2021 03:20:00 -0700 (PDT) MIME-Version: 1.0 References: <20210802043312.21711-1-hongtao.liu@intel.com> In-Reply-To: <20210802043312.21711-1-hongtao.liu@intel.com> From: Richard Biener Date: Mon, 2 Aug 2021 12:19:50 +0200 Message-ID: Subject: Re: [PATCH] Support cond_add/sub/mul/div for vector float/double. To: liuhongt Cc: GCC Patches Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Aug 2021 10:20:03 -0000 On Mon, Aug 2, 2021 at 6:33 AM liuhongt wrote: > > Hi: > This patch supports cond_add/sub/mul/div expanders for vector float/double. > There're still cond_fma/fms/fnms/fma/max/min/xor/ior/and left which I failed to figure out a testcase to validate them. > Also cond_add/sub/mul for vector integer. I think FMA can be verified by combining cond_mul and cond_add since the FMA recognizing code will try to match those up with cond_fma (plus the other variants). Eventually combine can handle this on RTL already. The max/min/ior/and will only show up with masked epilogues when vectorizing reductions. Richard. > > Bootstrap is ok, survive the regression test on x86_64-linux-gnu{-m32,}. > Pushed to trunk if there're no objections. > > gcc/ChangeLog: > > * config/i386/sse.md (cond_):New expander. > (cond_mul): Ditto. > (cond_div): Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/cond_op_addsubmuldiv_double-1.c: New test. > * gcc.target/i386/cond_op_addsubmuldiv_double-2.c: New test. > * gcc.target/i386/cond_op_addsubmuldiv_float-1.c: New test. > * gcc.target/i386/cond_op_addsubmuldiv_float-2.c: New test. > --- > gcc/config/i386/sse.md | 54 ++++++++++++ > .../i386/cond_op_addsubmuldiv_double-1.c | 31 +++++++ > .../i386/cond_op_addsubmuldiv_double-2.c | 85 +++++++++++++++++++ > .../i386/cond_op_addsubmuldiv_float-1.c | 9 ++ > .../i386/cond_op_addsubmuldiv_float-2.c | 4 + > 5 files changed, 183 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_double-1.c > create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_double-2.c > create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_float-1.c > create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_float-2.c > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index b5a08988590..8bf1764d3d5 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -1891,6 +1891,24 @@ (define_insn_and_split "*nabs2" > } > [(set_attr "isa" "noavx,noavx,avx,avx")]) > > +(define_expand "cond_" > + [(set (match_operand:VF 0 "register_operand") > + (vec_merge:VF > + (plusminus:VF > + (match_operand:VF 2 "vector_operand") > + (match_operand:VF 3 "vector_operand")) > + (match_operand:VF 4 "nonimm_or_0_operand") > + (match_operand: 1 "register_operand")))] > + " == 64 || TARGET_AVX512VL" > +{ > + emit_insn (gen_3_mask (operands[0], > + operands[2], > + operands[3], > + operands[4], > + operands[1])); > + DONE; > +}) > + > (define_expand "3" > [(set (match_operand:VF 0 "register_operand") > (plusminus:VF > @@ -1953,6 +1971,24 @@ (define_insn "_vm3" > (set_attr "prefix" "") > (set_attr "mode" "")]) > > +(define_expand "cond_mul" > + [(set (match_operand:VF 0 "register_operand") > + (vec_merge:VF > + (mult:VF > + (match_operand:VF 2 "vector_operand") > + (match_operand:VF 3 "vector_operand")) > + (match_operand:VF 4 "nonimm_or_0_operand") > + (match_operand: 1 "register_operand")))] > + " == 64 || TARGET_AVX512VL" > +{ > + emit_insn (gen_mul3_mask (operands[0], > + operands[2], > + operands[3], > + operands[4], > + operands[1])); > + DONE; > +}) > + > (define_expand "mul3" > [(set (match_operand:VF 0 "register_operand") > (mult:VF > @@ -2041,6 +2077,24 @@ (define_expand "div3" > } > }) > > +(define_expand "cond_div" > + [(set (match_operand:VF 0 "register_operand") > + (vec_merge:VF > + (div:VF > + (match_operand:VF 2 "register_operand") > + (match_operand:VF 3 "vector_operand")) > + (match_operand:VF 4 "nonimm_or_0_operand") > + (match_operand: 1 "register_operand")))] > + " == 64 || TARGET_AVX512VL" > +{ > + emit_insn (gen__div3_mask (operands[0], > + operands[2], > + operands[3], > + operands[4], > + operands[1])); > + DONE; > +}) > + > (define_insn "_div3" > [(set (match_operand:VF 0 "register_operand" "=x,v") > (div:VF > diff --git a/gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_double-1.c b/gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_double-1.c > new file mode 100644 > index 00000000000..1092cba9876 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_double-1.c > @@ -0,0 +1,31 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -march=skylake-avx512 -fdump-tree-vect" } */ > +/* { dg-final { scan-tree-dump ".COND_ADD" "vect" } } */ > +/* { dg-final { scan-tree-dump ".COND_SUB" "vect" } } */ > +/* { dg-final { scan-tree-dump ".COND_MUL" "vect" } } */ > +/* { dg-final { scan-tree-dump ".COND_RDIV" "vect" } } */ > + > +#ifndef NUM > +#define NUM 800 > +#endif > +#ifndef TYPE > +#define TYPE double > +#endif > + > +TYPE a[NUM], b[NUM], c[NUM], d[NUM], e[NUM], j[NUM]; > + > +#define BIN(OPNAME, OP) \ > + void \ > + __attribute__ ((noipa,optimize ("O3"))) \ > + foo_##OPNAME () \ > + { \ > + for (int i = 0; i != NUM; i++) \ > + if (b[i] < c[i]) \ > + a[i] = d[i] OP e[i]; \ > + } > + > + > +BIN (add, +); > +BIN (sub, -); > +BIN (mul, *); > +BIN (div, /); > diff --git a/gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_double-2.c b/gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_double-2.c > new file mode 100644 > index 00000000000..360891f3d21 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_double-2.c > @@ -0,0 +1,85 @@ > +/* { dg-do run } */ > +/* { dg-options "-O2 -mavx512vl -mprefer-vector-width=256" } */ > + > +#define AVX512VL > +#ifndef CHECK > +#define CHECK "avx512f-helper.h" > +#endif > + > +#include CHECK > + > +#include "cond_op_addsubmuldiv_double-1.c" > +#define BINO2(OPNAME, OP) \ > + void \ > + __attribute__ ((noipa,optimize ("O2"))) \ > + foo_o2_##OPNAME () \ > + { \ > + for (int i = 0; i != NUM; i++) \ > + if (b[i] < c[i]) \ > + j[i] = d[i] OP e[i]; \ > + } > + > + > +BINO2 (add, +); > +BINO2 (sub, -); > +BINO2 (mul, *); > +BINO2 (div, /); > + > +static void > +test_256 (void) > +{ > + int sign = -1; > + for (int i = 0; i != NUM; i++) > + { > + a[i] = 0.0; > + d[i] = i * 0.5; > + e[i] = i * i * 0.3 - i * 0.9 + 15.3; > + b[i] = i * 0.83; > + c[i] = b[i] + sign; > + sign *= -1; > + j[i] = b[i] < c[i] ? 1.0 : 0.0; > + } > + foo_add (); > + foo_o2_add (); > + for (int i = 0; i != NUM; i++) > + { > + if (a[i] != j[i]) > + abort (); > + a[i] = 0.0; > + j[i] = b[i] < c[i] ? 1.0 : 0.0; > + } > + > + foo_sub (); > + foo_o2_sub (); > + for (int i = 0; i != NUM; i++) > + { > + if (a[i] != j[i]) > + abort (); > + a[i] = 0.0; > + j[i] = b[i] < c[i] ? 1.0 : 0.0; > + } > + > + foo_mul (); > + foo_o2_mul (); > + for (int i = 0; i != NUM; i++) > + { > + if (a[i] != j[i]) > + abort (); > + a[i] = 0.0; > + j[i] = b[i] < c[i] ? 1.0 : 0.0; > + } > + > + foo_div (); > + foo_o2_div (); > + for (int i = 0; i != NUM; i++) > + { > + if (a[i] != j[i]) > + abort (); > + } > +} > + > +static void > +test_128 () > +{ > + > +} > diff --git a/gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_float-1.c b/gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_float-1.c > new file mode 100644 > index 00000000000..d4975271e26 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_float-1.c > @@ -0,0 +1,9 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -march=skylake-avx512 -DTYPE=float -fdump-tree-vect" } */ > +/* { dg-final { scan-tree-dump ".COND_ADD" "vect" } } */ > +/* { dg-final { scan-tree-dump ".COND_SUB" "vect" } } */ > +/* { dg-final { scan-tree-dump ".COND_MUL" "vect" } } */ > +/* { dg-final { scan-tree-dump ".COND_RDIV" "vect" } } */ > + > +#include "cond_op_addsubmuldiv_double-1.c" > + > diff --git a/gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_float-2.c b/gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_float-2.c > new file mode 100644 > index 00000000000..20ed737cbf3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/cond_op_addsubmuldiv_float-2.c > @@ -0,0 +1,4 @@ > +/* { dg-do run } */ > +/* { dg-options "-O2 -mavx512vl -mprefer-vector-width=256 -DTYPE=float" } */ > + > +#include "cond_op_addsubmuldiv_double-2.c" > -- > 2.18.1 >