From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by sourceware.org (Postfix) with ESMTPS id AD4A03858CDB for ; Mon, 26 Feb 2024 07:38:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AD4A03858CDB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org AD4A03858CDB Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::131 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708933102; cv=none; b=ccfCtEDGYMrwMy5jrepTVvKRAfR3Y1A7jQ4kM8dseSlIKwCJYT9jXztz9yjKYZiNxGwp4wWkd4GtA4aGcMTmWTV06Uc8p9rhFy47f2c/8WxDjUsIKrjggYJ5mnyvz4TPuJzBOH/JfbOmbkqQTy/RYOf8XOfsMZfAWZHCnfC8oAo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708933102; c=relaxed/simple; bh=5rX3FXb+2YbNOgyWqIhIiPVA2lF00vECQC7O5zDxzMA=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=tkIokuJoAZXgaIxSFSFrdHMRiftIP2ET7AJQ6sIHUGckHS+ckK2fnrr0kOdufs1o9X0rysvm50AwZdyGGebD6aNQPCQF+m2uPdeEkes65v4+/HAFa5B/2op0Pqqk1apGWdZgjMn0UtrMfAwGDTjSAV7RluU/sDK+EMsOk9xP7BA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-512d19e2cb8so4084893e87.0 for ; Sun, 25 Feb 2024 23:38:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1708933099; x=1709537899; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=oPPji1px2vAHwJgttXwnAuRb7BJr0X2dxiXEALaGao4=; b=DhnVpQxCuB8Anols12yEqDpH7JmsF1ggF+DyYwkstVmu1TtWoL02P1h2pQuxO3l4Kh jMOs/Opuc+yev+LCb1EzPvvsU3J3bf3UKftZqfiscX5sYCvFQM3wyb1/RmjU/D5554S/ 9fUSc+Yv7M7FZQxiFvzqasfwgj88GDYucaRuzf4FjsYMQtvPvkKFpY4K3YVIvqkJhM9O MC7JOW+8hcaBe3vPr6TfjiXoR3FJxSGE63LZQ0eRGIj+dLoHz+Vf9brQPPlAuzEYhtsh FeuRmQ09YQrvQDlEPGZg4YhZ6iB0i4fJHgmoNN3Pptbm48XcaW6ZpFBsqeSdvBMY5SSE mWjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708933099; x=1709537899; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oPPji1px2vAHwJgttXwnAuRb7BJr0X2dxiXEALaGao4=; b=UzDPM3+46ceD0mi2SD+F3yJBIg7nj6wsYbKbfMp1ysXaQmRfnX2/FsPTVrNLV/eRCa ft0fCHG+29vi3Ck3Pzp/+In5k2yCr8BeDa1KwyItYzD0VcqLcWB4KkxKxxHNe6eDi4Ka JF6IMo/zDHppvMinKHC7zY8YpCdu6m2E7USa0BpNpENyYXVdcrqS3BLkr+2VVty6IY/7 pnj07raDCEgWD2XkaDxRnJ9kKP86U7u9FTPPnHDksLGap2FixcXx+Zpm1dXef3URr/mJ F+9d9zZimbXJF8OVLGCU0Y48z+Du+0oIBaNj/bX1b3v/Y3BQi8VsWxkGFeBGCrIMXZWY kyvQ== X-Gm-Message-State: AOJu0YwxjEv+HLHKcPgpycyDsoMegixAK4XVQjPhd7D8GqUNlBpsaC+k 931rOLjCF7qJJOno1xqsK/TuMbBKI2BoSC6rkgAExOEZfIFmLPNIYGqqwoesLQeiz+94lBPYC3w UoJt2rE8qlgoLSlNFr5UEYGGWHXY= X-Google-Smtp-Source: AGHT+IFBu5rYftbLCO92H3ZdjPfQ07/ciambtXT/aHQ8sGfbC3wbDeF5e60X/YIkVmlaXNH9MD7rR3AePk019p5tNno= X-Received: by 2002:a05:6512:6d0:b0:512:fd8a:d0d0 with SMTP id u16-20020a05651206d000b00512fd8ad0d0mr1529225lff.28.1708933098675; Sun, 25 Feb 2024 23:38:18 -0800 (PST) MIME-Version: 1.0 References: <20240226032558.587912-1-pan2.li@intel.com> In-Reply-To: <20240226032558.587912-1-pan2.li@intel.com> From: Richard Biener Date: Mon, 26 Feb 2024 08:38:07 +0100 Message-ID: Subject: Re: [PATCH v1] RTL: Bugfix ICE after allow vector type in DSE To: pan2.li@intel.com Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, yanzhang.wang@intel.com, rdapp.gcc@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Feb 26, 2024 at 4:26=E2=80=AFAM wrote: > > From: Pan Li > > We allowed vector type for get_stored_val when read is less than or > equal to store in previous. Unfortunately, we missed to adjust the > validate_subreg part accordingly. For vector type, we don't need to > restrict the mode size is greater than the vector register size. > > Thus, for example when gen_lowpart from E_V2SFmode to E_V4QImode, it > will have NULL_RTX(of course ICE after that) because of the mode size > is less than vector register size. That also explain that gen_lowpart > from E_V8SFmode to E_V16QImode is valid here. > > This patch would like to remove the the restriction for vector mode, to > rid of the ICE when gen_lowpart because of validate_subreg fails. validate_subreg is a can of worms, can you try to fix the issue in DSE by avoiding to form the subreg in the first place? > The below test are passed for this patch: > > * The X86 bootstrap test. > * The fully riscv regression tests. > > gcc/ChangeLog: > > * emit-rtl.cc (validate_subreg): Bypass register size check > if the mode is vector. > > gcc/testsuite/ChangeLog: > > * gcc.dg/tree-ssa/ssa-fre-44.c: Add ftree-vectorize to trigger > the ICE. > * gcc.target/riscv/rvv/base/bug-6.c: New test. > > Signed-off-by: Pan Li > --- > gcc/emit-rtl.cc | 3 ++- > gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c | 2 +- > .../gcc.target/riscv/rvv/base/bug-6.c | 22 +++++++++++++++++++ > 3 files changed, 25 insertions(+), 2 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c > > diff --git a/gcc/emit-rtl.cc b/gcc/emit-rtl.cc > index 1856fa4884f..45c6301b487 100644 > --- a/gcc/emit-rtl.cc > +++ b/gcc/emit-rtl.cc > @@ -934,7 +934,8 @@ validate_subreg (machine_mode omode, machine_mode imo= de, > ; > /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_fi= eld > is the culprit here, and not the backends. */ > - else if (known_ge (osize, regsize) && known_ge (isize, osize)) > + else if (known_ge (isize, osize) && (known_ge (osize, regsize) > + || (VECTOR_MODE_P (imode) || VECTOR_MODE_P (omode)))) > ; > /* Allow component subregs of complex and vector. Though given the be= low > extraction rules, it's not always clear what that means. */ > diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c b/gcc/testsuite/g= cc.dg/tree-ssa/ssa-fre-44.c > index f79b4c142ae..624a00a4f32 100644 > --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c > +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-44.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O -fdump-tree-fre1" } */ > +/* { dg-options "-O -fdump-tree-fre1 -O3 -ftree-vectorize" } */ > > struct A { float x, y; }; > struct B { struct A u; }; > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c b/gcc/testsu= ite/gcc.target/riscv/rvv/base/bug-6.c > new file mode 100644 > index 00000000000..5bb00b8f587 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-6.c > @@ -0,0 +1,22 @@ > +/* Test that we do not have ice when compile */ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d -O3 -ftree-vectorize" } = */ > + > +struct A { float x, y; }; > +struct B { struct A u; }; > + > +extern void bar (struct A *); > + > +float > +f3 (struct B *x, int y) > +{ > + struct A p =3D {1.0f, 2.0f}; > + struct A *q =3D &x[y].u; > + > + __builtin_memcpy (&q->x, &p.x, sizeof (float)); > + __builtin_memcpy (&q->y, &p.y, sizeof (float)); > + > + bar (&p); > + > + return x[y].u.x + x[y].u.y; > +} > -- > 2.34.1 >