From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by sourceware.org (Postfix) with ESMTPS id 9B0423858D32 for ; Thu, 2 Nov 2023 08:22:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9B0423858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9B0423858D32 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::22e ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698913381; cv=none; b=K1hFzcMVKQ24lVcjvzWFZlqM84UdY5v9hJ7zyojef1v79ijMyxUH/yO4JeimU/bE7ImUNRX7l6Q85lCp6dJRENjbwraUGNLqDziJQ0HTS/xXLuIDu88IGExc6DRxRRzD2ZCM3q6Rj80OgWudQGLqzAsdlLvniI+wIea306fGvb0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698913381; c=relaxed/simple; bh=QLS8gUNjdXVVNu9HpZ4dB+5yViNSzSOu1nbn+dDrf/E=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=J5suJCjCACBaAN9UPMg/rAVBSmxIRUeG0yLd6T+mZdFA1G4TOc0qvgchxzyffw4P5XVkpEkvCRJBwdCocbhH4IRxlm6DBrNr8Yd37WA7La0djsrTCx/F1GZFX8SYHvwq7ABaHF8h4ZgvnT8NW7sEvspMPMN1urLQ0HufpdKGhxc= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2c515527310so9170431fa.2 for ; Thu, 02 Nov 2023 01:22:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1698913369; x=1699518169; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=u8xjz0aPHxUzxN/2aNrBXFBnWR28H9EzX3eZGY/SOY8=; b=RP9Q/7pbApzYQr11lAkDPLmo7vO+t9vdxfYc3oBOS0+ywkoZM/7I2lL5lxk+/jeI7o WkZDbQ3R8CdAx/x66h1Oc4OepdS72wB2LFP+8mZ0QCDN/IGu9O55pA3ljbUCAqd/UL+v iAVR9LwpBJQXuj3e2Ixhatd1eex6OAP/wn/c6G52hp6Nv+fUfg+9tMgmabatARjRaoPJ AHtlvODnPzjP951eWbvvjSFAuwOPS9BkBBkbl97YtiVYoa5rKyVmMuqMSJSBT5LdVubx ogxAQQeFJp3PV8R3gBKLI/RxFQTC+QYyV8xJ4WnDf8htg42hGgOd9JA9Qpd/QMPLGhFb KQvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698913369; x=1699518169; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u8xjz0aPHxUzxN/2aNrBXFBnWR28H9EzX3eZGY/SOY8=; b=jUQPAWd2IENQ7+ogsYsaUjHmA2kKJsHRW9ONeVICD8aZ9llP7IrDzD9vOTliFs/yQJ 1JSar9yXkLbXR/1+DfCo9VMsrSmXPr1F8AJgVfB7WSHSTHjT6yg0U5N44bjMFn4yC/PE 7HUbKTcnAWPj2AKAFm24fTVWXir+ELbbNxu+Y6eh6RgBuEh103HaHBMarxVGB85SGu90 jIrvA2mfwjWcaaOKJNrT3DozhMEgU7PgkKhUHoKLE4T+UMuUjCJf/rDraYaS5X5uU3xa GpRS4fwfzlAwtQ1e1ykNOEt36Ct/IMFAIhwcbkQtrfWD95qgIatjbkViF67VxUANsGuV lA7w== X-Gm-Message-State: AOJu0YwWMD8ftjD6VfMDzL9N51vn1v5eiB2/IgshcS7wjcGZe9YgGWnq yhEvZbvfjnmfphkbarNx2Fhk0oZxz4xqTx1jT48= X-Google-Smtp-Source: AGHT+IHrh1HqWamLNPZl8U/M+KSybh5vEF/8UCI5b5PgjlZSxz/Pz6bxvyTWQeuPbxdHndDGOWmqEd3ccucbamxeygE= X-Received: by 2002:ac2:46c7:0:b0:507:a383:fe18 with SMTP id p7-20020ac246c7000000b00507a383fe18mr13333859lfo.40.1698913368814; Thu, 02 Nov 2023 01:22:48 -0700 (PDT) MIME-Version: 1.0 References: <20231102031423.3751965-1-pan2.li@intel.com> In-Reply-To: <20231102031423.3751965-1-pan2.li@intel.com> From: Richard Biener Date: Thu, 2 Nov 2023 09:19:32 +0100 Message-ID: Subject: Re: [PATCH v1] EXPMED: Allow vector mode for DSE extract_low_bits [PR111720] To: pan2.li@intel.com Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, yanzhang.wang@intel.com, kito.cheng@gmail.com, jeffreyalaw@gmail.com, richard.sandiford@arm.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Nov 2, 2023 at 4:15=E2=80=AFAM wrote: > > From: Pan Li > > The extract_low_bits only try the scalar mode if the bitsize of > the mode and src_mode is not equal. When vector mode is given > from get_stored_val in DSE, it will always fail and return NULL_RTX. > > This patch would like to allow the vector mode in the extract_low_bits > if and only if the size of mode is less than or equals to the size of > the src_mode. > > Given below example code with --param=3Driscv-autovec-preference=3Dfixed-= vlmax. > > vuint8m1_t test () { > uint8_t arr[32] =3D { > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, > 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, > }; > > return __riscv_vle8_v_u8m1(arr, 32); > } > > Before this patch: > > test: > lui a5,%hi(.LANCHOR0) > addi sp,sp,-32 > addi a5,a5,%lo(.LANCHOR0) > li a3,32 > vl2re64.v v2,0(a5) > vsetvli zero,a3,e8,m1,ta,ma > vs2r.v v2,0(sp) <=3D=3D Unnecessary store to stack > vle8.v v1,0(sp) <=3D=3D Ditto > vs1r.v v1,0(a0) > addi sp,sp,32 > jr ra > > After this patch: > > test: > lui a5,%hi(.LANCHOR0) > addi a5,a5,%lo(.LANCHOR0) > li a4,32 > addi sp,sp,-32 > vsetvli zero,a4,e8,m1,ta,ma > vle8.v v1,0(a5) > vs1r.v v1,0(a0) > addi sp,sp,32 > jr ra > > Below tests are passed within this patch: > > * The x86 bootstrap and regression test. > * The aarch64 regression test. > * The risc-v regression test. > > PR target/111720 > > gcc/ChangeLog: > > * expmed.cc (extract_low_bits): Allow vector mode if the > mode size is less than or equal to src_mode. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/pr111720-0.c: New test. > * gcc.target/riscv/rvv/base/pr111720-1.c: New test. > * gcc.target/riscv/rvv/base/pr111720-10.c: New test. > * gcc.target/riscv/rvv/base/pr111720-2.c: New test. > * gcc.target/riscv/rvv/base/pr111720-3.c: New test. > * gcc.target/riscv/rvv/base/pr111720-4.c: New test. > * gcc.target/riscv/rvv/base/pr111720-5.c: New test. > * gcc.target/riscv/rvv/base/pr111720-6.c: New test. > * gcc.target/riscv/rvv/base/pr111720-7.c: New test. > * gcc.target/riscv/rvv/base/pr111720-8.c: New test. > * gcc.target/riscv/rvv/base/pr111720-9.c: New test. > > Signed-off-by: Pan Li > --- > gcc/expmed.cc | 44 ++++++++++++------- > .../gcc.target/riscv/rvv/base/pr111720-0.c | 18 ++++++++ > .../gcc.target/riscv/rvv/base/pr111720-1.c | 18 ++++++++ > .../gcc.target/riscv/rvv/base/pr111720-10.c | 18 ++++++++ > .../gcc.target/riscv/rvv/base/pr111720-2.c | 18 ++++++++ > .../gcc.target/riscv/rvv/base/pr111720-3.c | 18 ++++++++ > .../gcc.target/riscv/rvv/base/pr111720-4.c | 18 ++++++++ > .../gcc.target/riscv/rvv/base/pr111720-5.c | 18 ++++++++ > .../gcc.target/riscv/rvv/base/pr111720-6.c | 18 ++++++++ > .../gcc.target/riscv/rvv/base/pr111720-7.c | 21 +++++++++ > .../gcc.target/riscv/rvv/base/pr111720-8.c | 18 ++++++++ > .../gcc.target/riscv/rvv/base/pr111720-9.c | 15 +++++++ > 12 files changed, 227 insertions(+), 15 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c > > diff --git a/gcc/expmed.cc b/gcc/expmed.cc > index b294eabb08d..5db83fe638c 100644 > --- a/gcc/expmed.cc > +++ b/gcc/expmed.cc > @@ -2403,8 +2403,6 @@ extract_split_bit_field (rtx op0, opt_scalar_int_mo= de op0_mode, > rtx > extract_low_bits (machine_mode mode, machine_mode src_mode, rtx src) > { > - scalar_int_mode int_mode, src_int_mode; > - > if (mode =3D=3D src_mode) > return src; > > @@ -2437,22 +2435,38 @@ extract_low_bits (machine_mode mode, machine_mode= src_mode, rtx src) > return x; > } > > - if (!int_mode_for_mode (src_mode).exists (&src_int_mode) > - || !int_mode_for_mode (mode).exists (&int_mode)) > - return NULL_RTX; > + if (VECTOR_MODE_P (mode) && VECTOR_MODE_P (src_mode)) when there are integer modes for the vector modes you now go a different pa= th, a little less "regressing" would be to write it as if (int_mode_for_mode (src_mode).exists (&src_int_mode) && int_mode_for_mode (mode).exists (&int_mode)) { ... old code ... } else if (VECTOR_MODE_P (mode) && VECTOR_MODE_P (src_mode)) { ... new code ... } else return NULL_RTX; > + { > + if (maybe_gt (GET_MODE_BITSIZE (mode), GET_MODE_BITSIZE (src_mode)= ) > + || !targetm.modes_tieable_p (mode, src_mode)) > + return NULL_RTX; > > - if (!targetm.modes_tieable_p (src_int_mode, src_mode)) > - return NULL_RTX; > - if (!targetm.modes_tieable_p (int_mode, mode)) > - return NULL_RTX; > + /* For vector mode, only the bitsize (mode) <=3D bitsize (src_mod= e) and > + tieable is allowed here. */ > + src =3D gen_lowpart (mode, src); so you're really expecting to generate a subreg here? Given "vector register layout" isn't something that's very well defined I fear it's going to be difficult to guarantee the desired semantics of this function. IIRC powerpc64le has big-endian la= ne order for example. > + } > + else > + { > + scalar_int_mode int_mode, src_int_mode; > > - src =3D gen_lowpart (src_int_mode, src); > - if (!validate_subreg (int_mode, src_int_mode, src, > - subreg_lowpart_offset (int_mode, src_int_mode))) > - return NULL_RTX; > + if (!int_mode_for_mode (src_mode).exists (&src_int_mode) > + || !int_mode_for_mode (mode).exists (&int_mode)) > + return NULL_RTX; > + > + if (!targetm.modes_tieable_p (src_int_mode, src_mode)) > + return NULL_RTX; > + if (!targetm.modes_tieable_p (int_mode, mode)) > + return NULL_RTX; > + > + src =3D gen_lowpart (src_int_mode, src); > + if (!validate_subreg (int_mode, src_int_mode, src, > + subreg_lowpart_offset (int_mode, src_int_mode= ))) > + return NULL_RTX; > + > + src =3D convert_modes (int_mode, src_int_mode, src, true); > + src =3D gen_lowpart (mode, src); > + } > > - src =3D convert_modes (int_mode, src_int_mode, src, true); > - src =3D gen_lowpart (mode, src); > return src; > } > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c b/gcc/t= estsuite/gcc.target/riscv/rvv/base/pr111720-0.c > new file mode 100644 > index 00000000000..a61e94a6d98 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv64gcv -mabi=3Dlp64d -ftree-vectorize --p= aram=3Driscv-autovec-preference=3Dfixed-vlmax -Wno-psabi" } */ > + > +#include "riscv_vector.h" > + > +vuint8m1_t test () { > + uint8_t arr[32] =3D { > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + }; > + > + return __riscv_vle8_v_u8m1(arr, 32); > +} > + > +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c b/gcc/t= estsuite/gcc.target/riscv/rvv/base/pr111720-1.c > new file mode 100644 > index 00000000000..46efd7379ac > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv64gcv -mabi=3Dlp64d -ftree-vectorize --p= aram=3Driscv-autovec-preference=3Dfixed-vlmax -Wno-psabi" } */ > + > +#include "riscv_vector.h" > + > +vuint8m2_t test () { > + uint8_t arr[32] =3D { > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + }; > + > + return __riscv_vle8_v_u8m2(arr, 32); > +} > + > +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > +/* { dg-final { scan-assembler-not {vs[09]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\= )} } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c b/gcc/= testsuite/gcc.target/riscv/rvv/base/pr111720-10.c > new file mode 100644 > index 00000000000..8bebac219a6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv64gcv -mabi=3Dlp64d -ftree-vectorize --p= aram=3Driscv-autovec-preference=3Dfixed-vlmax -Wno-psabi" } */ > + > +#include "riscv_vector.h" > + > +vbool4_t test () { > + uint8_t arr[32] =3D { > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + }; > + > + return __riscv_vlm_v_b4(arr, 32); > +} > + > +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c b/gcc/t= estsuite/gcc.target/riscv/rvv/base/pr111720-2.c > new file mode 100644 > index 00000000000..47e4243e02e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv64gcv -mabi=3Dlp64d -ftree-vectorize --p= aram=3Driscv-autovec-preference=3Dfixed-vlmax -Wno-psabi" } */ > + > +#include "riscv_vector.h" > + > +vuint8m1_t test () { > + uint8_t arr[32] =3D { > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + }; > + > + return __riscv_vle8_v_u8m1(arr, 16); > +} > + > +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c b/gcc/t= estsuite/gcc.target/riscv/rvv/base/pr111720-3.c > new file mode 100644 > index 00000000000..5331e547ed3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv64gcv -mabi=3Dlp64d -ftree-vectorize --p= aram=3Driscv-autovec-preference=3Dfixed-vlmax -Wno-psabi" } */ > + > +#include "riscv_vector.h" > + > +vuint8m2_t test () { > + uint8_t arr[32] =3D { > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + }; > + > + return __riscv_vle8_v_u8m2(arr, 8); > +} > + > +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > +/* { dg-final { scan-assembler-not {vs[09]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\= )} } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c b/gcc/t= estsuite/gcc.target/riscv/rvv/base/pr111720-4.c > new file mode 100644 > index 00000000000..0c728f93514 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv64gcv -mabi=3Dlp64d -ftree-vectorize --p= aram=3Driscv-autovec-preference=3Dfixed-vlmax -Wno-psabi" } */ > + > +#include "riscv_vector.h" > + > +vuint8mf2_t test () { > + uint8_t arr[32] =3D { > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + }; > + > + return __riscv_vle8_v_u8mf2(arr, 32); > +} > + > +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c b/gcc/t= estsuite/gcc.target/riscv/rvv/base/pr111720-5.c > new file mode 100644 > index 00000000000..ccfc40cd382 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv64gcv -mabi=3Dlp64d -ftree-vectorize --p= aram=3Driscv-autovec-preference=3Dfixed-vlmax -Wno-psabi" } */ > + > +#include "riscv_vector.h" > + > +vuint8m2_t test () { > + uint8_t arr[32] =3D { > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + }; > + > + return __riscv_vle8_v_u8m2(arr, 4); > +} > + > +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > +/* { dg-final { scan-assembler-not {vs[09]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp\= )} } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c b/gcc/t= estsuite/gcc.target/riscv/rvv/base/pr111720-6.c > new file mode 100644 > index 00000000000..ce7ddbb99b2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv64gcv -mabi=3Dlp64d -ftree-vectorize --p= aram=3Driscv-autovec-preference=3Dfixed-vlmax -Wno-psabi" } */ > + > +#include "riscv_vector.h" > + > +vuint8m8_t test () { > + uint8_t arr[32] =3D { > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + }; > + > + return __riscv_vle8_v_u8m8(arr, 32); > +} > + > +/* { dg-final { scan-assembler-times {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(= sp\)} 1 } } */ > +/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(= sp\)} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c b/gcc/t= estsuite/gcc.target/riscv/rvv/base/pr111720-7.c > new file mode 100644 > index 00000000000..ac0100a1211 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c > @@ -0,0 +1,21 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv64gcv -mabi=3Dlp64d -ftree-vectorize --p= aram=3Driscv-autovec-preference=3Dfixed-vlmax -Wno-psabi" } */ > + > +#include "riscv_vector.h" > + > +vbool8_t test () { > + uint8_t arr[32] =3D { > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + 1, 2, 7, 1, 3, 4, 5, 3, > + 1, 0, 1, 2, 4, 4, 9, 9, > + }; > + > + vuint8m1_t varr =3D __riscv_vle8_v_u8m1(arr, 32); > + vuint8m1_t vand_m =3D __riscv_vand_vx_u8m1(varr, 1, 32); > + > + return __riscv_vreinterpret_v_u8m1_b8(vand_m); > +} > + > +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c b/gcc/t= estsuite/gcc.target/riscv/rvv/base/pr111720-8.c > new file mode 100644 > index 00000000000..b7ebef80954 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv64gcv -mabi=3Dlp64d -ftree-vectorize --p= aram=3Driscv-autovec-preference=3Dfixed-vlmax -Wno-psabi" } */ > + > +#include "riscv_vector.h" > + > +vfloat32m1_t test () { > + float arr[32] =3D { > + 1.0, 2.2, 7.8, 1.2, 3.3, 4.7, 5.5, 3.3, > + 1.0, 0.2, 1.8, 2.2, 4.3, 4.7, 9.5, 9.3, > + 1.0, 2.2, 7.8, 1.2, 3.3, 4.7, 5.5, 3.3, > + 1.0, 0.2, 1.8, 2.2, 4.3, 4.7, 9.5, 9.3, > + }; > + > + return __riscv_vle32_v_f32m1(arr, 32); > +} > + > +/* { dg-final { scan-assembler-not {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > +/* { dg-final { scan-assembler-not {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(sp= \)} } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c b/gcc/t= estsuite/gcc.target/riscv/rvv/base/pr111720-9.c > new file mode 100644 > index 00000000000..21fed06d201 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c > @@ -0,0 +1,15 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -march=3Drv64gcv -mabi=3Dlp64d -ftree-vectorize --p= aram=3Driscv-autovec-preference=3Dfixed-vlmax -Wno-psabi" } */ > + > +#include "riscv_vector.h" > + > +vfloat64m8_t test () { > + double arr[8] =3D { > + 1.0, 2.2, 7.8, 1.2, 3.3, 4.7, 5.5, 3.3, > + }; > + > + return __riscv_vle64_v_f64m8(arr, 4); > +} > + > +/* { dg-final { scan-assembler-times {vle[0-9]+\.v\s+v[0-9]+,\s*[0-9]+\(= sp\)} 1 } } */ > +/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*[0-9]+\(= sp\)} 1 } } */ > -- > 2.34.1 >