From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by sourceware.org (Postfix) with ESMTPS id C29F23910B55 for ; Mon, 19 Dec 2022 07:44:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C29F23910B55 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-lf1-x135.google.com with SMTP id p36so12362349lfa.12 for ; Sun, 18 Dec 2022 23:44:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=DMqR1ZaBpVo5dIiHdEDRLYXrBFYoy+V3xboYWIfUZp4=; b=EbMkU9TbHkvcgI25ofkb4JWuTVPLZBaBQnj1b8YemSPClh5rqGCr1jbA8TqmJU78Jz o0GZknSsoLzBmgFOEB9JwdULnzeG/aunftH8v77kU84EkPaMg0hftZUCl+4rEmBeAPV7 AdCYUrxETM12WfbKRo+S/T4UZzrFsyA7NqX6S8bf4gbPx7Rrmu4AAO/M7rm0IQqO547g EBDaHh5KeVTre1ywvlPfEusDGQhHtoNa6BLLHUVCkASsom3TtDBXxbl8XmCpsN96y7zI IzDAjqzgg8o0pmRywrpAaRgUSg1XN7mIEfgNFXc7lVD4FduVvam1C4o0Id0nnEoPULw+ gEzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DMqR1ZaBpVo5dIiHdEDRLYXrBFYoy+V3xboYWIfUZp4=; b=LzDU6t5IcW55j5aO60nHMsDzk7jjH2jSVIsrxlH2glmUbJRmAlSwp5y9jDlRCTuOzs js9TTn6C+dXUCDKAbMTHxPwIhYtfWxzuwLqE0q/mD+mOtq9p06/c7a6995tkb7EQFS/U DjF2XAyv/ZILTQaop9miCzuCDJejsJmfHS1HoOxZGONkOemUh6AXtOCh15ME9ZKKo8Bq VuYwFz9XLgqMtYl25GoaW+el4B+yAGtkgUvxm8yubyxdr02tatCz9SDHu7Kwj3BLUrF8 YU5p9F5Xze34uc9fJ6weQF6R9hmzf3gV708xxiaJ0PexGBy3lpMmUFnk2Uvx8ChlsWH6 LAwQ== X-Gm-Message-State: ANoB5plSR7HAHynJ6MTt+ornbtLHrWitgKueDfvnKFBEBESI546i5oV/ zPP+vA2ufeBZrcuyjNApJlXdaZXxUqFfT1Rjx9k= X-Google-Smtp-Source: AA0mqf59GbMh9orZetplWlGTngWUpDpB4xBP1FBYXsz8FLkbCJyLD8PxHkX18f0cQat+CYmVGABnqBf7Cr37N2Ugdj0= X-Received: by 2002:a05:6512:376c:b0:4ad:70c1:de61 with SMTP id z12-20020a056512376c00b004ad70c1de61mr32304308lft.509.1671435894103; Sun, 18 Dec 2022 23:44:54 -0800 (PST) MIME-Version: 1.0 References: <20221214064825.240605-1-juzhe.zhong@rivai.ai> <190019d9-155b-e0d1-43d3-d9baae96a2cc@gmail.com> <27D1642B23C2C0D1+2022121709442960704166@rivai.ai> <75eb29fd-6449-e2d1-2702-d297373cecf3@gmail.com> In-Reply-To: <75eb29fd-6449-e2d1-2702-d297373cecf3@gmail.com> From: Richard Biener Date: Mon, 19 Dec 2022 08:44:40 +0100 Message-ID: Subject: Re: [PATCH] RISC-V: Fix RVV mask mode size To: Jeff Law Cc: =?UTF-8?B?6ZKf5bGF5ZOy?= , gcc-patches , "kito.cheng" , palmer Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sat, Dec 17, 2022 at 2:54 AM Jeff Law via Gcc-patches wrote: > > > > On 12/16/22 18:44, =E9=92=9F=E5=B1=85=E5=93=B2 wrote: > > Yes, VNx4DF only has 4 bit in mask mode in case of load and store. > > For example vlm or vsm we will load store 8-bit ??? (I am not sure > > hardward can load store 4bit,but I am sure it definetly not load store > > the whole register size) > Most likely than not you end up loading a larger quantity with the high > bits zero'd. Interesting that we're using a packed model. I'd been > told it was fairly expensive to implement in hardware relative to teh > cost of implementing the sparse model. Since the masks are extra inputs if you use a packed model you need to wire less bits into the execution units for the masks which I guess is actually cheaper. Yes, producing the masks might be more complicated. > > So ideally it should be model more accurate. However, since GCC assumes > > that 1 BOOL is 1-byte, the only thing I do is to model mask mode as > > smallest as possible. > > Maybe in the future, I can support 1BOOL for 1-bit?? I am not sure sinc= e > > it will need to change GCC framework. > I'm a bit confused by this. GCC can support single bit bools, though > ports often extend them to 8 bits or more for computational efficiency > purposes. At least that's the case in general. Is there something > particularly special about masks & bools that's causing problems? The only "issue" might be with 4, 2 and 1 bit masks which would have a size of 8 bits but a precision of less that endianess might play a role. Btw, this is all similar to AVX512 where we even don't use vector BI modes but integer modes for the mask which then becomes QImode for 1, 2, 4 and 8 bit masks and HImode for 16, SImode for 32 and DImode for 64 bit masks. Richard. > Jeff