From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by sourceware.org (Postfix) with ESMTPS id DEFBB3858C54 for ; Wed, 29 Mar 2023 08:11:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DEFBB3858C54 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-lj1-x233.google.com with SMTP id z42so15166781ljq.13 for ; Wed, 29 Mar 2023 01:11:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680077470; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=MMF50OIbeWzh9lBnLg5oNA3UlZ5C/+dwVxsftpyYXbE=; b=AgyyL4ej0aMcbpvm9/0C9P0u2Qi9dO4RpNRq9uW/ympZnv8g+rBMgIZ3ItsTn3DhwY Y50MifiFIEenTC4fFSlbFjbnEwpog5Tinga4Zm2PXOkBZpDq7Fc2PzKaubz81twC6nOm PWuVLalmdLoWH3tPOUzW32QmjCBlGrA5ApvhoeU1ToVXbhapYfw2WUZ0trKOkv7RExjU Co1CgnGFnIezHIyi/VL1Ys+u+OJOPkSKHs8Db/9KfIlJDLQWCxLif+GUDZ/FJubC9pAr QrIMocSlGWP9WTYf2EcVyhBS2aArJcN7Lkaf+dfOhyUY4PIALS9/CBLvjtyF9bAYm+hZ d6OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680077470; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MMF50OIbeWzh9lBnLg5oNA3UlZ5C/+dwVxsftpyYXbE=; b=xKlx2VfnmaywoySFMNXIhtSz91Wac33l9Z2bKFIk9ZsKETaPuVliqd66Rngoa1a8sA Y63lvgB0MA2J6AbXhEPEhukhcJEcMaS98SwHxHGNbawiAuSwkv2WFIqDAwiMvDtcWOOt mawFTc9rI1M/mcEBctVNtYxAKX9ZOYVL+Dmm/RzHEr9xzHK7Kul9Hsn+YKwAXWoh/JZi 4q50cfng5q1jYxUnScJy9X616OO83KePia/GaKbdPDi4nwEQ9gtIBRkYmmsbLAj2Foms /O9Z+VcNQrkbkOlU1u2mYRqk/9nv1zQUeIClBWsthTjb+DAujNU56FrjiNtwdTtW9YWj 700g== X-Gm-Message-State: AAQBX9cD08+63LxfLmaWAH7r9552FPjMCsCkOjlfWzZXIqrnr3uEji4l 10+E8siILF3QnHe6DSbEACtujr8uxyKTtn+ovcc= X-Google-Smtp-Source: AKy350YhPeJaPTHwEPaOXZdn1Koo3u/MHyRjrCGHmUlXTPMXo/ozdnLi2a2b6Kd85RbbzGQrzsszGvdNFRPMpKK+FFI= X-Received: by 2002:a2e:9848:0:b0:2a6:de0:79af with SMTP id e8-20020a2e9848000000b002a60de079afmr514138ljj.10.1680077470106; Wed, 29 Mar 2023 01:11:10 -0700 (PDT) MIME-Version: 1.0 References: <20230329075222.2888608-1-pan2.li@intel.com> In-Reply-To: <20230329075222.2888608-1-pan2.li@intel.com> From: Richard Biener Date: Wed, 29 Mar 2023 10:10:29 +0200 Message-ID: Subject: Re: [PATCH] [RISC-V]: Bugfix for RVV vbool*_t vn_reference_equal. To: pan2.li@intel.com Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, kito.cheng@sifive.com, rguenther@suse.de, yanzhang.wang@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Mar 29, 2023 at 9:55=E2=80=AFAM Pan Li via Gcc-patches wrote: > > From: Pan Li > > In most architecture the precision_size of vbool*_t types are caculated > like as the multiple of the type size. For example: > precision_size =3D type_size * 8 (aka, bit count per bytes). > > Unfortunately, some architecture like RISC-V will adjust the precision_si= ze > for the vbool*_t in order to align the ISA. For example as below. > type_size =3D [1, 1, 1, 1, 2, 4, 8] > precision_size =3D [1, 2, 4, 8, 16, 32, 64] > > Then the precision_size of RISC-V vbool*_t will not be the multiple of th= e > type_size. This PATCH try to enrich this case when comparing the vn_refer= ence. > > Given we have the below code: > void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out= ) { > vbool8_t v1 =3D *(vbool8_t*)in; > vbool16_t v2 =3D *(vbool16_t*)in; > > *(vbool8_t*)(out + 100) =3D v1; > *(vbool16_t*)(out + 200) =3D v2; > } > > Before this PATCH: > csrr t0,vlenb > slli t1,t0,1 > csrr a3,vlenb > sub sp,sp,t1 > slli a4,a3,1 > add a4,a4,sp > addi a2,a1,100 > vsetvli a5,zero,e8,m1,ta,ma > sub a3,a4,a3 > vlm.v v24,0(a0) > vsm.v v24,0(a2) > vsm.v v24,0(a3) > addi a1,a1,200 > csrr t0,vlenb > vsetvli a4,zero,e8,mf2,ta,ma > slli t1,t0,1 > vlm.v v24,0(a3) > vsm.v v24,0(a1) > add sp,sp,t1 > jr ra > > After this PATCH: > addi a3,a1,100 > vsetvli a4,zero,e8,m1,ta,ma > addi a1,a1,200 > vlm.v v24,0(a0) > vsm.v v24,0(a3) > vsetvli a5,zero,e8,mf2,ta,ma > vlm.v v24,0(a0) > vsm.v v24,0(a1) > ret > > PR 109272 > > gcc/ChangeLog: > > * tree-ssa-sccvn.cc (vn_reference_eq): > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/pr108185-4.c: > * gcc.target/riscv/rvv/base/pr108185-5.c: > * gcc.target/riscv/rvv/base/pr108185-6.c: > --- > .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +- > .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +- > .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +- > gcc/tree-ssa-sccvn.cc | 13 +++++++++++++ > 4 files changed, 16 insertions(+), 3 deletions(-) > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/t= estsuite/gcc.target/riscv/rvv/base/pr108185-4.c > index ea3c360d756..e70284fada8 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c > @@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in, int8_t *= restrict out) { > /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf4,\s*ta,\s*ma} 1 } } */ > /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf8,\s*ta,\s*ma} 1 } } */ > /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 12 } } */ > -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 15 } } */ > +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 12 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/t= estsuite/gcc.target/riscv/rvv/base/pr108185-5.c > index 9fc659d2402..575a7842cdf 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c > @@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in, int8_t = * restrict out) { > /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf4,\s*ta,\s*ma} 1 } } */ > /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf8,\s*ta,\s*ma} 1 } } */ > /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 12 } } */ > -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 14 } } */ > +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 12 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/t= estsuite/gcc.target/riscv/rvv/base/pr108185-6.c > index 98275e5267d..95a11d37016 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c > @@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in, int8_t = * restrict out) { > /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf2,\s*ta,\s*ma} 1 } } */ > /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e= 8,\s*mf8,\s*ta,\s*ma} 1 } } */ > /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 12 } } */ > -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 13 } } */ > +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 12 } } */ > diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc > index 6b8d38b270c..c6dfa8fd9a3 100644 > --- a/gcc/tree-ssa-sccvn.cc > +++ b/gcc/tree-ssa-sccvn.cc > @@ -799,6 +799,19 @@ vn_reference_eq (const_vn_reference_t const vr1, con= st_vn_reference_t const vr2) > && (TYPE_PRECISION (vr2->type) > !=3D TREE_INT_CST_LOW (TYPE_SIZE (vr2->type)))) > return false; > + else if (VECTOR_BOOLEAN_TYPE_P (vr1->type) > + && VECTOR_BOOLEAN_TYPE_P (vr2->type) > + && expressions_equal_p (TYPE_SIZE (vr1->type), > + TYPE_SIZE (vr2->type)) > + && TYPE_PRECISION (vr1->type) !=3D TYPE_PRECISION (vr2->type)) > + /* For the vbool*_t types in most architectures, the precision size = is > + caculated as the multiple of the type size. For example, > + precision_size =3D type_size * 8 (aka, bit count per bytes). > + Unfortunately, some architecture like RISC-V will adjust the > + precision for the vbool*_t in order to align the ISA and the > + precision will not be the multiple of the type size. Thus, enric= h > + the type comparation for this case here. */ > + return false; I would prefer if you write it cheaper, like else if (VECTOR_BOOLEAN_TYPE_P (vr1->type) && VECTOR_BOOLEAN_TYPE_P (vr2->type)) { /* Vector boolean types can have padding, verify we are dealing wi= th the same number of elements. */ if (TYPE_VECTOR_SUBPARTS (vr1->type) !=3D TYPE_VECTOR_SUBPARTS (vr2->type)) return false; } there is IMHO no reason to compare TYPE_SIZE again. Richard. > > i =3D 0; > j =3D 0; > -- > 2.34.1 >