From: Richard Biener <richard.guenther@gmail.com>
To: Jakub Jelinek <jakub@redhat.com>
Cc: "Jiang, Haochen" <haochen.jiang@intel.com>,
ZiNgA BuRgA <zingaburga@hotmail.com>,
Hongtao Liu <crazylht@gmail.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: Intel AVX10.1 Compiler Design and Support
Date: Tue, 22 Aug 2023 10:35:30 +0200 [thread overview]
Message-ID: <CAFiYyc387aVc6LYg9wyAph6Eufk8Mi6GsM++5=00=nLTYx2xnw@mail.gmail.com> (raw)
In-Reply-To: <ZORzAI/QK1c1NEKu@tucnak>
On Tue, Aug 22, 2023 at 10:34 AM Jakub Jelinek <jakub@redhat.com> wrote:
>
> On Tue, Aug 22, 2023 at 09:36:15AM +0200, Richard Biener via Gcc-patches wrote:
> > I think internally we should have conditional 512bit support work across
> > AVX512 and AVX10.
> >
> > I also think it makes sense to _internally_ have AVX10.1 (10.1!) just
> > enable the respective AVX512 features. AVX10.2 would then internally
> > cover the ISA extensions added in 10.2 only. Both would reduce the
> > redundancy and possibly make providing inter-operation between
> > AVX10.1 (10.1!) and AVX512 to the user easier. I see AVX 10.1 (10.1!)
> > just as "re-branding" latest AVX512, so we should treat it that way
> > (making it an alias to the AVX512 features).
> >
> > Whether we want allow -mavx10.1 -mno-avx512cd or whether
> > we only allow the "positive" -mavx512f -mavx512... (omitting avx512cd)
> > is an entirely separate
> > question. But I think to not wreck the core idea (more interoperability,
> > here between small/big cores) we absolutely have to
> > provide a subset of avx10.1 but with disabled 512bit vectors which
> > effectively means AVX512 with disabled 512bit support.
>
> Agreed. And I still think -mevex512 vs. -mno-evex512 is the best option
> name to represent whether the effective ISA set allows 512-bit vectors or
> not.
Works for me. Note it also implies mask regs are SImode, not DImode,
not sure if that relates to evex more than mask reg encodings are all evex ...
> I think -mavx10.1 -mno-avx512cd should be fine. And, -mavx10.1-256
> option IMHO should be in the same spirit to all the others a positive enablement,
> not both positive (enable avx512{f,cd,bw,dq,...} and negative (disallow
> 512-bit vectors). So, if one uses -mavx512f -mavx10.1-256, because the
> former would allow 512-bit vectors, the latter shouldn't disable those again
> because it isn't a -mno-* option. Sure, instructions which are specific to
> AVX10.1 (aren't present in any currently existing AVX512* ISA set) might be
> enabled only in 128/256 bit variants if we differentiate that level.
> But, if one uses -mavx2 -mavx10.1-256, because no AVX512* has been enabled
> it can enable all the AVX10.1 implied AVX512* parts without EVEX.512.
>
> Jakub
>
next prev parent reply other threads:[~2023-08-22 8:37 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-08 7:13 Haochen Jiang
2023-08-08 7:13 ` [PATCH 1/3] Initial support for AVX10.1 Haochen Jiang
2023-08-16 2:29 ` Hongtao Liu
2023-08-08 7:13 ` [PATCH 2/3] Emit a warning when disabling AVX512 with AVX10 enabled or disabling AVX10 with AVX512 enabled Haochen Jiang
2023-08-16 2:30 ` Hongtao Liu
2023-08-08 7:13 ` [PATCH 3/3] Emit a warning when AVX10 options conflict in vector width Haochen Jiang
2023-08-16 2:30 ` Hongtao Liu
2023-08-08 7:19 ` [PATCH 1/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins Haochen Jiang
2023-08-08 7:20 ` [PATCH 2/6] " Haochen Jiang
2023-08-08 7:20 ` [PATCH 3/6] " Haochen Jiang
2023-08-08 7:20 ` [PATCH 4/6] " Haochen Jiang
2023-08-08 7:20 ` [PATCH 5/6] " Haochen Jiang
2023-08-08 7:20 ` [PATCH 6/6] " Haochen Jiang
2023-08-16 2:36 ` Hongtao Liu
2023-08-08 7:42 ` Intel AVX10.1 Compiler Design and Support Jakub Jelinek
2023-08-08 8:14 ` Jiang, Haochen
2023-08-08 12:44 ` Richard Biener
2023-08-09 2:06 ` Hongtao Liu
2023-08-09 2:08 ` Hongtao Liu
2023-08-09 6:30 ` Jiang, Haochen
2023-08-08 19:55 ` Joseph Myers
2023-08-09 1:21 ` Hongtao Liu
2023-08-09 2:14 ` Hongtao Liu
2023-08-09 2:18 ` Hongtao Liu
2023-08-09 3:59 ` Wang, Phoebe
2023-08-09 20:43 ` Joseph Myers
2023-08-09 20:49 ` Jakub Jelinek
2023-08-10 12:36 ` Phoebe Wang
2023-08-10 12:45 ` Richard Biener
2023-08-10 13:12 ` Phoebe Wang
2023-08-10 13:30 ` Jan Beulich
2023-08-10 13:52 ` Richard Biener
2023-08-10 14:15 ` Jiang, Haochen
2023-08-10 15:08 ` Zhang, Annita
2023-08-10 15:18 ` Jakub Jelinek
2023-08-10 22:16 ` Joseph Myers
2023-08-09 4:01 ` Phoebe Wang
2023-08-09 5:37 ` Richard Biener
2023-08-09 6:24 ` Jiang, Haochen
2023-08-09 8:14 ` Florian Weimer
2023-08-09 8:24 ` Hongtao Liu
2023-08-09 7:17 ` Jan Beulich
2023-08-09 7:38 ` Hongtao Liu
2023-08-09 8:04 ` Jan Beulich
2023-08-09 9:15 ` Florian Weimer
2023-08-09 10:15 ` Hongtao Liu
2023-08-09 10:17 ` Zhang, Annita
2023-08-09 13:54 ` Michael Matz
2023-08-09 14:34 ` Zhang, Annita
2023-08-10 15:08 ` Jiang, Haochen
2023-08-10 16:00 ` Jakub Jelinek
2023-08-19 22:44 ` ZiNgA BuRgA
2023-08-20 5:44 ` Richard Biener
2023-08-21 1:19 ` Hongtao Liu
2023-08-21 7:36 ` Richard Biener
2023-08-21 8:09 ` Jakub Jelinek
2023-08-21 8:28 ` Hongtao Liu
2023-08-21 8:37 ` Jakub Jelinek
2023-08-21 8:46 ` Hongtao Liu
2023-08-21 9:34 ` Richard Biener
2023-08-21 9:36 ` Richard Biener
2023-08-21 9:50 ` Hongtao Liu
2023-08-21 9:26 ` ZiNgA BuRgA
2023-08-22 3:20 ` Jiang, Haochen
2023-08-22 7:36 ` Richard Biener
2023-08-22 8:34 ` Jakub Jelinek
2023-08-22 8:35 ` Richard Biener [this message]
2023-08-22 8:52 ` Jiang, Haochen
2023-08-22 9:23 ` Richard Biener
2023-08-22 13:02 ` Hongtao Liu
2023-08-22 13:16 ` Jakub Jelinek
2023-08-22 13:23 ` Richard Biener
2023-08-22 13:35 ` Hongtao Liu
2023-08-22 13:54 ` Jakub Jelinek
2023-08-22 14:35 ` Hongtao Liu
2023-08-22 15:01 ` Jakub Jelinek
2023-08-23 1:57 ` Jiang, Haochen
2023-08-23 2:19 ` Hongtao Liu
2023-08-23 6:47 ` Jiang, Haochen
2023-08-23 8:16 ` Jakub Jelinek
2023-08-23 8:27 ` Hongtao Liu
2023-08-23 7:32 ` Richard Biener
2023-08-23 8:03 ` Jiang, Haochen
2023-08-23 8:31 ` Jakub Jelinek
2023-08-23 8:47 ` Hongtao Liu
2023-08-23 8:24 ` Hongtao Liu
2023-08-22 14:39 ` Hongtao Liu
2023-08-21 7:49 ` ZiNgA BuRgA
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