From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by sourceware.org (Postfix) with ESMTPS id A26003858D32 for ; Fri, 10 Nov 2023 10:15:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A26003858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A26003858D32 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::233 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699611329; cv=none; b=q2PX9VBbPL/kCW1EylEioB4QrPvabQg1xqU+lMNLUm8kSn5Um4Pakf/X3Z9hehbHCGDy2OADT768GjTgCuhHVq2kS8oBHi0NIsgh4V7rqZj0hpRdek3OD+Vwut8MQ7jHwRn5BT7DT9yIyquTiGkVVNzm9X7Bb93inP1jIa+SJJI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699611329; c=relaxed/simple; bh=7bWkcpMFClp3bfQaokAqAGOmJV0cIpz16WBxvVlxcDg=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=xUNqfiGe2OKxiN+Sa3i4L9f1eZ+4eRdhEIFFDHs6wH8nRltxpFyOAfFMPRDP7WhFSGZXoW+pca2VwR/VNCOWf9143d4jTQ2hXUnTatLY0v3Om7Ab8jgms3ceDUi2NzXii4pp4gQxnroFU7vSolqAUTaP6ri0lVfGkNbYxmOYqH4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2c5028e5b88so25138321fa.3 for ; Fri, 10 Nov 2023 02:15:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1699611325; x=1700216125; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=iSdHaGIRSYh183NzD/aQm4pb2l9sxrTlnBnmn5OC1AM=; b=akTrT6o8IlARfGBBGI9uomRdCOJ0ekWZfikGsd7vyoCESObrh1HQkZNTgzA1wr54Hr 5Jo0q15fegFy09Y8JeX2M6cyDF1IbU14CvlK2JhOOvrGSTVC3dz3I++FrT5+zMw74UJZ z048Z6FppFJWyz4FJnWaabE7/6o6YYdZnxYbpN0GWFMDQe4lOkiZYwNqfOyBq/XCARSp 3C+JEC9hYjHcuGX/YKqTDCv2JQ/KfEl04hsqK1i/NgLqi03Ck3Zdjz84ezWewxQyaXFA /spI5QZ+vKa5lgszAKZfc9pcyGkMwOlIKbgh2oXShK+rdgpnVBFJrmI5HYLtG15fDToA NcNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699611325; x=1700216125; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iSdHaGIRSYh183NzD/aQm4pb2l9sxrTlnBnmn5OC1AM=; b=Y/zGPBRtXWf7jqJK07bJT/kgFd2XePbMf4ijAKFaDCyFRaT+jSn078j3L4gpNkzQ5P 1w0jvqmI389n3NCdZgN0aftrekOfXxEWBKGFvRNS1hPa1WGrI9dFbiLnhXtCvzrU2gdg WEkdbHE3ViM1CquHIorz4STymzkPVOTiikoKbJtbhKDbA2zml0XqABXLD/AlWQVclEkN 5miygrQt+j59PutdqdiaenMjxMheSNJyHtJJqngHUiXHB/fczft6ipxQas74AW8aOkl7 pUPkvJqrjaYahGxW5I3R9D8LSlR+iEDYegni3Kkie4EVVzKuD4ZbwpwLxEKWVod1X1lY Ik3Q== X-Gm-Message-State: AOJu0YxlfrR1r+uaMuK0nftZtxKKpcJrf+JTE7aRMQ4TZ7n30/HUv3Uq v1vZ5mjLzGPFHPFM1W/T3R+2ybLX2tZEflFUI3a4znBp X-Google-Smtp-Source: AGHT+IEFGBbhxL2L5CXHEYyKiG6BflnODWz6L/UrL64+v0Gb9iOOVs+pKgEHmMNz+rWoXmWJEWqaRohsOlL0M2z3sYI= X-Received: by 2002:a05:6512:4dc:b0:500:7cab:efc3 with SMTP id w28-20020a05651204dc00b005007cabefc3mr3350633lfq.11.1699611324863; Fri, 10 Nov 2023 02:15:24 -0800 (PST) MIME-Version: 1.0 References: <20231110014158.371690-1-haochen.jiang@intel.com> In-Reply-To: <20231110014158.371690-1-haochen.jiang@intel.com> From: Richard Biener Date: Fri, 10 Nov 2023 11:15:13 +0100 Message-ID: Subject: Re: [RFC] Intel AVX10.1 Compiler Design and Support To: Haochen Jiang Cc: gcc-patches@gcc.gnu.org, hongtao.liu@intel.com, ubizjak@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Nov 10, 2023 at 2:42=E2=80=AFAM Haochen Jiang wrote: > > Hi all, > > This RFC patch aims to add AVX10.1 options. After we added -m[no-]evex512 > support, it makes a lot easier to add them comparing to the August versio= n. > Detail for AVX10 is shown below: > > Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specificat= ion > It describes the Intel Advanced Vector Extensions 10 Instruction Set > Architecture. > https://cdrdv2.intel.com/v1/dl/getContent/784267 > > The Converged Vector ISA: Intel Advanced Vector Extensions 10 Technical P= aper > It provides introductory information regarding the converged vector ISA: = Intel > Advanced Vector Extensions 10. > https://cdrdv2.intel.com/v1/dl/getContent/784343 > > Our proposal is to take AVX10.1-256 and AVX10.1-512 as two "virtual" ISAs= in > the compiler. AVX10.1-512 will imply AVX10.1-256. They will not enable > anything at first. At the end of the option handling, we will check wheth= er > the two bits are set. If AVX10.1-256 is set, we will set the AVX512 relat= ed > ISA bits. AVX10.1-512 will further set EVEX512 ISA bit. > > It means that AVX10 options will be separated from the existing AVX512 an= d the > newly added -m[no-]evex512 options. AVX10 and AVX512 options will control > (enable/disable/set vector size) the AVX512 features underneath independe= ntly. > If there=E2=80=99s potential overlap or conflict between AVX10 and AVX512= options, > some rules are provided to define the behavior, which will be described b= elow. > > avx10.1 option will be provided as an alias of avx10.1-256. > > In the future, the AVX10 options will imply like this: > > AVX10.1-256 <---- AVX10.1-512 > ^ ^ > | | > > AVX10.2-256 <---- AVX10.2-512 > ^ ^ > | | > > AVX10.3-256 <---- AVX10.3-512 > ^ ^ > | | > > Each of them will have its own option to enable/disabled corresponding > features. The alias avx10.x will also be provided. > > As mentioned in August version RFC, since we lean towards the adoption of > AVX10 instead of AVX512 from now on, we don=E2=80=99t recommend users to = combine the > AVX10 and legacy AVX512 options. I wonder whether adoption could be made easier by also providing a -mavx10[.0] level that removes some of the more obscure sub-ISA requirement= s to cover more existing implementations (I'd not add -mavx10.0-512 here). I'd require only skylake-AVX512 features here, basically all non-KNL AVX512 CPUs should have a "virtual" AVX10 level that allows to use that feature se= t, restricted to 256bits so future AVX10-256 implementations can handle it as well as all existing (and relevant, which excludes KNL) AVX512 implementations. Otherwise AVX10 is really a hard sell (as AVX512 was originally). > However, we would like to introduce some > simple rules for user when it comes to combination. > > 1. Enabling AVX10 and AVX512 at the same command line with different vect= or > size will lead to a warning message. The behavior of the compiler will be > enabling AVX10 with longer, i.e., 512 bit vector size. > > If the vector sizes are the same (e.g. -mavx10.1-256 -mavx512f -mno-evex5= 12, > -mavx10.1-512 -mavx512f), it will be valid with the corresponding vector = size. > > 2. -mno-avx10.1 option can=E2=80=99t disable any features enabled by AVX5= 12 options or > impact the vector size, and vice versa. The compiler will emit warnings i= f > necessary. > > For the auto dispatch support including function multi versioning, functi= on > attribute usage, the behavior will be identical to compiler options. > > If you have any questions, feel free to ask in this thread. > > Thx, > Haochen > >