From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by sourceware.org (Postfix) with ESMTPS id 743783858C2C for ; Thu, 25 May 2023 06:52:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 743783858C2C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2af2b74d258so2198551fa.3 for ; Wed, 24 May 2023 23:52:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684997557; x=1687589557; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=jrsrOAtqRWEdAQ2iogaUkO9nnoC5IqadwCxyM9OVtq8=; b=dyR3xsjb9f/IQ3vVYTXHayw6Y8xIMJf6t+betoRq6Yw1vjLms1CovcgjKx6JNa2h8z vktrwgnhJuMrs3xzAce3AXs12MwEtHS/z5QpSMkTO0EZBTWuP5oukyqTE0dMZ/1wqQT5 fZJBhibe5QC0b7ObAnsx0GMCLVNzZown+rvl46zHe6WBsi/KxgydjMAEyaO6Q0K9lTpS EJN3VXhsrjDLPhmGaelAKi+4rh8UO4oExkKznn+DDRB4Er9m2Wedbw5AvdsjXLkh3QO1 9B6Y6+8MJ49C7K8z842h4Ff+x/qpyNNAA5/bTDpJ2kZhp919yQw+3U489vCo427TIoUx mwlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684997557; x=1687589557; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jrsrOAtqRWEdAQ2iogaUkO9nnoC5IqadwCxyM9OVtq8=; b=aJY+rO+g05laGRVfgcgQcvI+4dWbCHrxtNyhEMEE/zO9sHSxKLOvOGAw0YgsynqrU0 stjKoPbzgPUk61LVBlQRcCkAgF80Tc/spehYjLx4m+6AmqhythUzd3ki2lAlrrsVfxA0 +/FN7XGLg4veueQnO3kcDRkss3qzOG3/iN9uwVUupzF9B2JSvpz9h3Rwl0EfaDP4Dtjc W2LCknIxo+Spxwp3nCHx1FbgZ4e6D8wonV2opJ5KMmYuvOEuA17zsvhzKGM6xBh1UF/8 OK68Q8L+2dnClfXEWEuiVO6WR628HY5ZeGseD1NDeoVQy8Lz+O2VMp8q2AuUeD04HXR9 MH8w== X-Gm-Message-State: AC+VfDwcIuQijmqoJszJ+xXBedQ8jR962wMcb1kaVjnJ25PSD5FVk1Dg 8bXLlvqbXOCfWvI8fODxTkC7erWtb7dyztnR9NAEk4O5/WU= X-Google-Smtp-Source: ACHHUZ7Fftb2DglvgA0SF6BB6YMsmzuXT8wRm4DtpWL0e4kgQeQWdXEoqD/iSdjysL26IDFYJkKokWUKJe6KjL2IV/0= X-Received: by 2002:a2e:b0d2:0:b0:2af:2786:2712 with SMTP id g18-20020a2eb0d2000000b002af27862712mr746842ljl.25.1684997556607; Wed, 24 May 2023 23:52:36 -0700 (PDT) MIME-Version: 1.0 References: <4b477e8c-f8e6-5587-23ed-540f0c28ea05@ispras.ru> In-Reply-To: <4b477e8c-f8e6-5587-23ed-540f0c28ea05@ispras.ru> From: Richard Biener Date: Thu, 25 May 2023 08:50:29 +0200 Message-ID: Subject: Re: [PATCH] doc: clarify semantics of vector bitwise shifts To: Alexander Monakov Cc: gcc-patches Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, May 24, 2023 at 8:36=E2=80=AFPM Alexander Monakov wrote: > > > On Wed, 24 May 2023, Richard Biener via Gcc-patches wrote: > > > I=E2=80=99d have to check the ISAs what they actually do here - it of c= ourse depends > > on RTL semantics as well but as you say those are not strictly defined = here > > either. > > Plus, we can add the following executable test to the testsuite: Yeah, that's probably a good idea. I think your documentation change with the added sentence about the truncation is OK. Note we have /* Shift operations for shift and rotate. Shift means logical shift if done on an unsigned type, arithmetic shift if done on a signed type. The second operand is the number of bits to shift by; it need not be the same type as the first operand and result. Note that the result is undefined if the second operand is larger than or equal to the first operand's type size. The first operand of a shift can have either an integer or a (non-integer) fixed-point type. We follow the ISO/IEC TR 18037:2004 semantics for the latter. Rotates are defined for integer types only. */ DEFTREECODE (LSHIFT_EXPR, "lshift_expr", tcc_binary, 2) in tree.def which implies short << 24 is undefined behavior (similar wording in generic.texi). The rtl docs say nothing about behavior but I think the semantics should carry over. That works for x86 even for scalar instructions working on GPRs (masking is applied but fixed to 5 or 6 bits even for QImode or HImode shifts). Note that when we make these shifts well-defined there's also arithmetic on signed types smaller than int (which again doesn't exist in C) where overflow invokes undefined behavior in the middle-end. Unless we want to change that as well this is somewhat inconsistent then. There's also the issue that C 'int' is defined by INT_TYPE_SIZE and thus target dependent which makes what is undefined and what not target dependent. Richard. > #include > > #define CHECK(TYPE, WIDTH, OP, COUNT, INVERT) \ > { \ > typedef TYPE vec __attribute__((vector_size(WIDTH))); \ > \ > static volatile vec zero; \ > vec tmp =3D (zero-2) OP (COUNT); \ > vec ref =3D INVERT zero; \ > if (__builtin_memcmp(&tmp, &ref, sizeof tmp)) \ > __builtin_abort(); \ > } > > int main(void) > { > CHECK( uint8_t, 16, <<, 8, ) > CHECK( uint8_t, 16, <<, 31, ) > CHECK( uint8_t, 16, >>, 8, ) > CHECK( uint8_t, 16, >>, 31, ) > CHECK( int8_t, 16, <<, 8, ) > CHECK( int8_t, 16, <<, 31, ) > CHECK( int8_t, 16, >>, 8, ~) > CHECK( int8_t, 16, >>, 31, ~) > CHECK(uint16_t, 16, <<, 16, ) > CHECK(uint16_t, 16, <<, 31, ) > CHECK(uint16_t, 16, >>, 16, ) > CHECK(uint16_t, 16, >>, 31, ) > CHECK( int16_t, 16, <<, 16, ) > CHECK( int16_t, 16, <<, 31, ) > CHECK( int16_t, 16, >>, 16, ~) > CHECK( int16_t, 16, >>, 31, ~) > // Per-lane-variable shifts: > CHECK( uint8_t, 16, <<, zero+8, ) > CHECK( uint8_t, 16, <<, zero+31, ) > CHECK( uint8_t, 16, >>, zero+8, ) > CHECK( uint8_t, 16, >>, zero+31, ) > CHECK( int8_t, 16, <<, zero+8, ) > CHECK( int8_t, 16, <<, zero+31, ) > CHECK( int8_t, 16, >>, zero+8, ~) > CHECK( int8_t, 16, >>, zero+31, ~) > CHECK(uint16_t, 16, <<, zero+16, ) > CHECK(uint16_t, 16, <<, zero+31, ) > CHECK(uint16_t, 16, >>, zero+16, ) > CHECK(uint16_t, 16, >>, zero+31, ) > CHECK( int16_t, 16, <<, zero+16, ) > CHECK( int16_t, 16, <<, zero+31, ) > CHECK( int16_t, 16, >>, zero+16, ~) > CHECK( int16_t, 16, >>, zero+31, ~) > > // Repeat for WIDTH=3D32 and WIDTH=3D64 > } > > Alexander