From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by sourceware.org (Postfix) with ESMTPS id 173E13858D1E for ; Thu, 9 Nov 2023 11:44:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 173E13858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 173E13858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::130 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699530290; cv=none; b=GDLdEADw9CssLs+anwrFHPadpiABLPYsus8xrRfghSvcsx7w9vyO05AGMzmJQXGax4RBgusteS0gg0x9hNwh5a6sZV/h5kLAiiRcxA4BgDUDYs43MWWw88BodWeI7U5XTdDXVWXrMXdDW5/Y0aCq2fjJm/ldh3WSb+EBju+S+d8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699530290; c=relaxed/simple; bh=SvS9yvub+/LFTe4RJOu3suYTKPehVdYsEYVA771zafU=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=UPEHbv64LHV7MEjLY9GXoPh18Q6Sd+KojCNqAHJ4hYjAr5O5APXCPh9094AVAxfLZtHPkkD+zPMkm+4khZ4o0lloMA3YWf2KJk+b7rU+m3IXLiBy4aRoIt190TfH7IWPcKWU03VDDrayoE2+o1JN0r6C9pHHe88/SVOHN75fCUE= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-5079f6efd64so882757e87.2 for ; Thu, 09 Nov 2023 03:44:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1699530287; x=1700135087; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=hpnrz1oKqhVQ9mLSXCrxa3p6b1Sj650tzNdKwhx8bGw=; b=ZEXeEPs4T7Lyk3W9a0drFHCDXS2KYNXgPc92V/k6SStbIKPXWHiMggbNmsNPJn+ZWp UDBHXx+E6l+VnK+Vfbw8mON/pvBQwe/opi2TDZsWsa8+2Vh9ffMoiaIrMiTAmxatqg7O VdxhZXyE/qvhHvu/ngRSNTkxrXmTdeJNI56HvG4w4k7U8mkqMBPy6VlE073Vaob7Swdt BaMqXtUUzs//OTL7Y1vmYE0dUT4yCzWBxYWBz4Ohd3M2ntxfg4/aLcT2kdKRPWtBsxkE ttM3yLCp4HsGE2FHwMcJXx0sNa7O51LVoze0kEtbTva4XMUlvAnfPZ5TP+FFFgakwAFu TXxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699530287; x=1700135087; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hpnrz1oKqhVQ9mLSXCrxa3p6b1Sj650tzNdKwhx8bGw=; b=a9JMqiNxggIslcMsnvKoqAWRuV108///O5Z2l6qW5BK7hl5p7/wwKaMYVFhUkH9TK2 xwZFk27unhk92jbe8adX8tcExbAKsU2RBdVO49Uga36mEIkpaWkfKdWrwlY9w3QosG+s EiItvOB0n1NK3Nqm0j/ZhGM/EWtupfaMf0CnM8vuWThSu9Y5zhOmy49syalxjApJsdOP ZuvYFd8QDItxp/Pi3r2lGIoQeG3TBCcNqy+N2LTQLX37Sl7iw3gW+xhpyLlrtuO56k9c 7jY8W6G48f1VEShredKWXoFzDEgQf+Sg/N7zSBeqvWjIKDGTAGtV+1dp/We+Dots2Cl9 gk5Q== X-Gm-Message-State: AOJu0YxeiqYeP1uzUwYUDIp95rALxHPavK6qZs7AVov9rXRpc3k2H2BM 3KLagdGIDRpRtME7E3HB6MuihBga00XIPFfG+gY= X-Google-Smtp-Source: AGHT+IFehLImm3BUA4+nD/ZPPRCwILSCQTWTEY/t9BKnkcN3rNxEGj+2mnP3k0ks47YR9V3skvooogKJguYksy2oq1s= X-Received: by 2002:ac2:44c5:0:b0:504:30eb:f2ac with SMTP id d5-20020ac244c5000000b0050430ebf2acmr1097339lfm.68.1699530287118; Thu, 09 Nov 2023 03:44:47 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Richard Biener Date: Thu, 9 Nov 2023 12:41:22 +0100 Message-ID: Subject: Re: [PATCH, expand] Call misaligned memory reference in expand_builtin_return [PR112417] To: HAO CHEN GUI Cc: gcc-patches , Segher Boessenkool , David , "Kewen.Lin" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Nov 9, 2023 at 6:43=E2=80=AFAM HAO CHEN GUI = wrote: > > Hi, > This patch modifies expand_builtin_return and make it call > expand_misaligned_mem_ref to load unaligned memory. The memory reference > pointed by void* pointer might be unaligned, so expanding it with > unaligned move optabs is safe. > > The new test case illustrates the problem. rs6000 doesn't have > unaligned vector load instruction with VSX disabled. When calling > builtin_return, it shouldn't load the memory to vector register by > unaligned load instruction directly. It should store it to an on stack > variable by extract_bit_field then load to return register from stack > by aligned load instruction. > > Bootstrapped and tested on x86 and powerpc64-linux BE and LE with no > regressions. Is this OK for trunk? I'm not sure if the testcase is valid though? @defbuiltin{{void} __builtin_return (void *@var{result})} This built-in function returns the value described by @var{result} from the containing function. You should specify, for @var{result}, a value returned by @code{__builtin_apply}. @enddefbuiltin I don't see __builtin_apply being used here? Richard. > Thanks > Gui Haochen > > ChangeLog > expand: Call misaligned memory reference in expand_builtin_return > > expand_builtin_return loads memory to return registers. The memory might > be unaligned compared to the mode of the registers. So it should be > expanded by unaligned move optabs if the memory reference is unaligned. > > gcc/ > PR target/112417 > * builtins.cc (expand_builtin_return): Call > expand_misaligned_mem_ref for loading unaligned memory reference. > * builtins.h (expand_misaligned_mem_ref): Declare. > * expr.cc (expand_misaligned_mem_ref): No longer static. > > gcc/testsuite/ > PR target/112417 > * gcc.target/powerpc/pr112417.c: New. > > patch.diff > diff --git a/gcc/builtins.cc b/gcc/builtins.cc > index cb90bd03b3e..b879eb88b7c 100644 > --- a/gcc/builtins.cc > +++ b/gcc/builtins.cc > @@ -1816,7 +1816,12 @@ expand_builtin_return (rtx result) > if (size % align !=3D 0) > size =3D CEIL (size, align) * align; > reg =3D gen_rtx_REG (mode, INCOMING_REGNO (regno)); > - emit_move_insn (reg, adjust_address (result, mode, size)); > + rtx tmp =3D adjust_address (result, mode, size); > + unsigned int align =3D MEM_ALIGN (tmp); > + if (align < GET_MODE_ALIGNMENT (mode)) > + tmp =3D expand_misaligned_mem_ref (tmp, mode, 1, align, > + NULL, NULL); > + emit_move_insn (reg, tmp); > > push_to_sequence (call_fusage); > emit_use (reg); > diff --git a/gcc/builtins.h b/gcc/builtins.h > index 88a26d70cd5..a3d7954ee6e 100644 > --- a/gcc/builtins.h > +++ b/gcc/builtins.h > @@ -157,5 +157,7 @@ extern internal_fn replacement_internal_fn (gcall *); > > extern bool builtin_with_linkage_p (tree); > extern int type_to_class (tree); > +extern rtx expand_misaligned_mem_ref (rtx, machine_mode, int, unsigned i= nt, > + rtx, rtx *); > > #endif /* GCC_BUILTINS_H */ > diff --git a/gcc/expr.cc b/gcc/expr.cc > index ed4dbb13d89..b0adb35a095 100644 > --- a/gcc/expr.cc > +++ b/gcc/expr.cc > @@ -9156,7 +9156,7 @@ expand_cond_expr_using_cmove (tree treeop0 ATTRIBUT= E_UNUSED, > If the result can be stored at TARGET, and ALT_RTL is non-NULL, > then *ALT_RTL is set to TARGET (before legitimziation). */ > > -static rtx > +rtx > expand_misaligned_mem_ref (rtx temp, machine_mode mode, int unsignedp, > unsigned int align, rtx target, rtx *alt_rtl) > { > diff --git a/gcc/testsuite/gcc.target/powerpc/pr112417.c b/gcc/testsuite/= gcc.target/powerpc/pr112417.c > new file mode 100644 > index 00000000000..ef82fc82033 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr112417.c > @@ -0,0 +1,12 @@ > +/* { dg-do compile { target { has_arch_pwr7 } } } */ > +/* { dg-options "-mno-vsx -maltivec -O2" } */ > + > +void * foo (void * p) > +{ > + if (p) > + __builtin_return (p); > +} > + > +/* Ensure that unaligned load is generated via stack load/store. */ > +/* { dg-final { scan-assembler {\mstw\M} { target { ! has_arch_ppc64 } }= } } */ > +/* { dg-final { scan-assembler {\mstd\M} { target has_arch_ppc64 } } } *= /