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From: Richard Biener <richard.guenther@gmail.com>
To: Robin Dapp <rdapp.gcc@gmail.com>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH] internal-fn: Do not force vcond operand to reg.
Date: Mon, 13 May 2024 09:53:29 +0200	[thread overview]
Message-ID: <CAFiYyc3WqZUAd+V7ORXJKuvytgbgKG6qLxij9PmKOo_G7Z103A@mail.gmail.com> (raw)
In-Reply-To: <3ff9db2b-012f-4311-afa7-314d0b50f976@gmail.com>

On Mon, May 13, 2024 at 8:18 AM Robin Dapp <rdapp.gcc@gmail.com> wrote:
>
> > How does this make a difference in the end?  I'd expect say forwprop to
> > fix things?
>
> In general we try to only add the masking "boilerplate" of our
> instructions at split time so fwprop, combine et al. can do their
> work uninhibited of it (and we don't need numerous
> (if_then_else ... (if_then_else) ...) combinations in our patterns).
> A vec constant we expand directly to a masked representation, though
> which makes further simplification difficult.  I can experiment with
> changing that if preferred.
>
> My thinking was, however, that for other operations like binops we
> directly emit the right variant via expand_operands without
> forcing to a reg and don't even need to fwprop so I wanted to
> imitate that.

Ah, so yeah, it probably makes sense for constants.  Btw,
there's prepare_operand which I think might be better for
its CONST_INT handling?  I can also see we usually do not
bother with force_reg, the force_reg was added with the
initial r6-4696-ga414c77f2a30bb already.

What happens if we simply remove all of the force_reg here?

Thanks,
Richard.

> Regards
>  Robin
>

  reply	other threads:[~2024-05-13  7:53 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-10 13:17 Robin Dapp
2024-05-10 13:21 ` Richard Biener
2024-05-13  6:18   ` Robin Dapp
2024-05-13  7:53     ` Richard Biener [this message]
2024-05-13 14:14       ` Robin Dapp
2024-05-13 14:19         ` Richard Biener
2024-05-17 10:35           ` Robin Dapp

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