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From: Richard Biener <richard.guenther@gmail.com>
To: Lehua Ding <lehua.ding@rivai.ai>
Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai,
	kito.cheng@gmail.com,  rdapp.gcc@gmail.com, palmer@rivosinc.com,
	jeffreyalaw@gmail.com
Subject: Re: [PATCH V2 0/3] RISC-V: Add an experimental vector calling convention
Date: Thu, 10 Aug 2023 09:43:03 +0200	[thread overview]
Message-ID: <CAFiYyc3Y8EZpAqrJxwbmiGzwMzqj3==fka4gk5s7Rv_w6C2sLw@mail.gmail.com> (raw)
In-Reply-To: <20230810070345.1623064-1-lehua.ding@rivai.ai>

On Thu, Aug 10, 2023 at 9:04 AM Lehua Ding <lehua.ding@rivai.ai> wrote:
>
> Hi RISC-V folks,
>
> This patch implement the proposal of RISC-V vector calling convention[1] and
> this feature can be enabled by `--param=riscv-vector-abi` option. Currently,
> all vector type arguments and return values are pass by reference. With this
> patch, these arguments and return values can pass through vector registers.
> Currently only vector types defined in the RISC-V Vector Extension Intrinsic Document[2]
> are supported. GNU-ext vector types are unsupported for now since the
> corresponding proposal was not presented.
>
> The proposal introduce a new calling convention variant, functions which follow
> this variant need follow the bellow vector register convention.
>
> | Name    | ABI Mnemonic | Meaning                      | Preserved across calls?
> =================================================================================
> | v0      |              | Argument register            | No
> | v1-v7   |              | Callee-saved registers       | Yes
> | v8-v23  |              | Argument registers           | No
> | v24-v31 |              | Callee-saved registers       | Yes
>
> If a functions follow this vector calling convention, then the function symbole
> must be annotated with .variant_cc directive[3] (used to indicate that it is a
> calling convention variant).
>
> This implementation split into three parts, each part corresponds to a sub-patch.
>
> - Part-1: Select suitable vector regsiters for vector type arguments and return
>   values according to the proposal.
> - Part-2: Allocate frame area for callee-saved vector registers and save/restore
>   them in prologue and epilogue.
> - Part-3: Generate .variant_cc directive for vector function in assembly code.

Just to mention at some point you want to think about the OpenMP SIMD ABI which
includes a mangling scheme but would also open up to have different
calling conventions.
So please keep that usage case in mind, possibly allowing the vector
calling convention
to be required for this.  Also note there's 'inbranch' variants which
require passing
a mask - your table above doesn't list any mask registers (in case
those exist in RISC-V).

Richard.

> Best,
> Lehua
>
> [1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389
> [2] https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#type-system
> [3] https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops
>
> Lehua Ding (3):
>   RISC-V: Part-1: Select suitable vector registers for vector type args
>     and returns
>   RISC-V: Part-2: Save/Restore vector registers which need to be
>     preversed
>   RISC-V: Part-3: Output .variant_cc directive for vector function
>
>  gcc/config/riscv/riscv-protos.h               |   4 +
>  gcc/config/riscv/riscv-sr.cc                  |  12 +-
>  gcc/config/riscv/riscv-vector-builtins.cc     |  10 +
>  gcc/config/riscv/riscv.cc                     | 505 ++++++++++++++++--
>  gcc/config/riscv/riscv.h                      |  40 ++
>  gcc/config/riscv/riscv.md                     |  43 +-
>  gcc/config/riscv/riscv.opt                    |   5 +
>  .../riscv/rvv/base/abi-call-args-1-run.c      | 127 +++++
>  .../riscv/rvv/base/abi-call-args-1.c          | 197 +++++++
>  .../riscv/rvv/base/abi-call-args-2-run.c      |  34 ++
>  .../riscv/rvv/base/abi-call-args-2.c          |  27 +
>  .../riscv/rvv/base/abi-call-args-3-run.c      | 260 +++++++++
>  .../riscv/rvv/base/abi-call-args-3.c          | 116 ++++
>  .../riscv/rvv/base/abi-call-args-4-run.c      | 145 +++++
>  .../riscv/rvv/base/abi-call-args-4.c          | 111 ++++
>  .../riscv/rvv/base/abi-call-error-1.c         |  11 +
>  .../riscv/rvv/base/abi-call-return-run.c      | 127 +++++
>  .../riscv/rvv/base/abi-call-return.c          | 197 +++++++
>  .../riscv/rvv/base/abi-call-variant_cc.c      |  39 ++
>  .../rvv/base/abi-callee-saved-1-fixed-1.c     |  85 +++
>  .../rvv/base/abi-callee-saved-1-fixed-2.c     |  85 +++
>  .../riscv/rvv/base/abi-callee-saved-1.c       |  87 +++
>  .../riscv/rvv/base/abi-callee-saved-2.c       | 117 ++++
>  23 files changed, 2322 insertions(+), 62 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-error-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c
>
> --
> 2.36.3
>

  parent reply	other threads:[~2023-08-10  7:44 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-10  7:03 Lehua Ding
2023-08-10  7:03 ` [PATCH V2 1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns Lehua Ding
2023-08-10  7:03 ` [PATCH V2 2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed Lehua Ding
2023-08-10  7:03 ` [PATCH V2 3/3] RISC-V: Part-3: Output .variant_cc directive for vector function Lehua Ding
2023-08-10  7:43 ` Richard Biener [this message]
2023-08-10  8:08   ` [PATCH V2 0/3] RISC-V: Add an experimental vector calling convention Lehua Ding

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