[PATCH, rs6000] (v3) Fold vector shifts in GIMPLE

[PATCH, rs6000] (v3) Fold vector shifts in GIMPLE

[Will Schmidt]

Hi, 

Add support for early expansion of vector shifts.  Including
vec_sl (shift left), vec_sr (shift right),
vec_sra (shift right algebraic), vec_rl (rotate left).
Part of this includes adding the vector shift right instructions to
the list of those instructions having an unsigned second argument.

The VSR (vector shift right) folding is a bit more complex than
the others. This is due to requiring arg0 be unsigned before the
gimple RSHIFT_EXPR assignment is built, which is required for an
algebraic shift.

[V2 update] Guard the folding of left shifts with TYPE_OVERFLOW_WRAPS.
Add -fwrapv test variations for the left shifts.

[V3 update] Rework the vector shift right folding logic to use the
gimple_build convenience routines.  Add a #include of ssa-propagate.h
to get at the update_call_from_tree() function.

I sniff-tested the latest changes on Power8, with good results.  Full
regtest running.  OK for trunk?


[gcc]

	2017-06-13  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* config/rs6000/rs6000.c: Add include of ssa-propagate.h for
	update_call_from_tree().
	(rs6000_gimple_fold_builtin): Add handling
	for early expansion of vector shifts (sl,sr,sra,rl).
	(builtin_function_type): Add vector shift right instructions
	to the unsigned argument list.
    
[gcc/testsuite]

	2017-06-13  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* testsuite/gcc.target/powerpc/fold-vec-shift-char.c: New.
	* testsuite/gcc.target/powerpc/fold-vec-shift-int.c: New.
	* testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c: New.
	* testsuite/gcc.target/powerpc/fold-vec-shift-short.c: New.
	* testsuite/gcc.target/powerpc/fold-vec-shift-left.c: New.
	* testsuite/gcc.target/powerpc/fold-vec-shift-left-fwrapv.c: New.
	* testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c: New.
	* testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong.c: New.

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 63ca2d1..a88fc18 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -77,6 +77,7 @@
 #endif
 #include "case-cfn-macros.h"
 #include "ppc-auxv.h"
+#include "tree-ssa-propagate.h"
 
 /* This file should be included last.  */
 #include "target-def.h"
@@ -16588,6 +16589,76 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
 	gsi_replace (gsi, g, true);
 	return true;
       }
+    /* Flavors of vec_rotate_left.  */
+    case ALTIVEC_BUILTIN_VRLB:
+    case ALTIVEC_BUILTIN_VRLH:
+    case ALTIVEC_BUILTIN_VRLW:
+    case P8V_BUILTIN_VRLD:
+      {
+	arg0 = gimple_call_arg (stmt, 0);
+	arg1 = gimple_call_arg (stmt, 1);
+	lhs = gimple_call_lhs (stmt);
+	gimple *g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+      }
+  /* Flavors of vector shift right algebraic.
+   * vec_sra{b,h,w} -> vsra{b,h,w}.  */
+    case ALTIVEC_BUILTIN_VSRAB:
+    case ALTIVEC_BUILTIN_VSRAH:
+    case ALTIVEC_BUILTIN_VSRAW:
+    case P8V_BUILTIN_VSRAD:
+      {
+	arg0 = gimple_call_arg (stmt, 0);
+	arg1 = gimple_call_arg (stmt, 1);
+	lhs = gimple_call_lhs (stmt);
+	gimple *g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+      }
+   /* Flavors of vector shift left.
+    * builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}.  */
+    case ALTIVEC_BUILTIN_VSLB:
+    case ALTIVEC_BUILTIN_VSLH:
+    case ALTIVEC_BUILTIN_VSLW:
+    case P8V_BUILTIN_VSLD:
+      {
+	arg0 = gimple_call_arg (stmt, 0);
+	if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
+	    && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
+	      return false;
+	arg1 = gimple_call_arg (stmt, 1);
+	lhs = gimple_call_lhs (stmt);
+	gimple *g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, arg1);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+      }
+    /* Flavors of vector shift right.  */
+    case ALTIVEC_BUILTIN_VSRB:
+    case ALTIVEC_BUILTIN_VSRH:
+    case ALTIVEC_BUILTIN_VSRW:
+    case P8V_BUILTIN_VSRD:
+      {
+	arg0 = gimple_call_arg (stmt, 0);
+	arg1 = gimple_call_arg (stmt, 1);
+	lhs = gimple_call_lhs (stmt);
+	gimple_seq stmts = NULL;
+	/* convert arg0 to unsigned.  */
+	tree arg0_unsigned
+	   = gimple_build (&stmts, VIEW_CONVERT_EXPR,
+			   unsigned_type_for (TREE_TYPE (arg0)), arg0);
+	tree res
+	   = gimple_build (&stmts, RSHIFT_EXPR,
+			   TREE_TYPE (arg0_unsigned), arg0_unsigned, arg1);
+	/* convert result back to the lhs type.  */
+	res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
+	gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
+	update_call_from_tree (gsi, res);
+	return true;
+      }
     default:
       break;
     }
@@ -18090,6 +18161,14 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
       h.uns_p[2] = 1;
       break;
 
+	/* unsigned second arguments (vector shift right).  */
+    case ALTIVEC_BUILTIN_VSRB:
+    case ALTIVEC_BUILTIN_VSRH:
+    case ALTIVEC_BUILTIN_VSRW:
+    case P8V_BUILTIN_VSRD:
+      h.uns_p[2] = 1;
+      break;
+
     default:
       break;
     }
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-char.c
new file mode 100644
index 0000000..ebe91e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-char.c
@@ -0,0 +1,66 @@
+/* Verify that overloaded built-ins for vec_sl with char
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+//# vec_sl  - shift left
+//# vec_sr  - shift right
+//# vec_sra - shift right algebraic
+//# vec_rl  - rotate left
+
+vector signed char
+testsl_signed (vector signed char x, vector unsigned char y)
+{
+  return vec_sl (x, y);
+}
+
+vector unsigned char
+testsl_unsigned (vector unsigned char x, vector unsigned char y)
+{
+  return vec_sl (x, y);
+}
+
+vector signed char
+testsr_signed (vector signed char x, vector unsigned char y)
+{
+  return vec_sr (x, y);
+}
+
+vector unsigned char
+testsr_unsigned (vector unsigned char x, vector unsigned char y)
+{
+  return vec_sr (x, y);
+}
+
+vector signed char
+testsra_signed (vector signed char x, vector unsigned char y)
+{
+  return vec_sra (x, y);
+}
+
+vector unsigned char
+testsra_unsigned (vector unsigned char x, vector unsigned char y)
+{
+  return vec_sra (x, y);
+}
+
+vector signed char
+testrl_signed (vector signed char x, vector unsigned char y)
+{
+  return vec_rl (x, y);
+}
+
+vector unsigned char
+testrl_unsigned (vector unsigned char x, vector unsigned char y)
+{
+  return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vslb" 2 } } */
+/* { dg-final { scan-assembler-times "vsrb" 2 } } */
+/* { dg-final { scan-assembler-times "vsrab" 2 } } */
+/* { dg-final { scan-assembler-times "vrlb" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-int.c
new file mode 100644
index 0000000..e9c5fe1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-int.c
@@ -0,0 +1,61 @@
+/* Verify that overloaded built-ins for vec_sl with int
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed int
+testsl_signed (vector signed int x, vector unsigned int y)
+{
+  return vec_sl (x, y);
+}
+
+vector unsigned int
+testsl_unsigned (vector unsigned int x, vector unsigned int y)
+{
+  return vec_sl (x, y);
+}
+
+vector signed int
+testsr_signed (vector signed int x, vector unsigned int y)
+{
+  return vec_sr (x, y);
+}
+
+vector unsigned int
+testsr_unsigned (vector unsigned int x, vector unsigned int y)
+{
+  return vec_sr (x, y);
+}
+
+vector signed int
+testsra_signed (vector signed int x, vector unsigned int y)
+{
+  return vec_sra (x, y);
+}
+
+vector unsigned int
+testsra_unsigned (vector unsigned int x, vector unsigned int y)
+{
+  return vec_sra (x, y);
+}
+
+vector signed int
+testrl_signed (vector signed int x, vector unsigned int y)
+{
+  return vec_rl (x, y);
+}
+
+vector unsigned int
+testrl_unsigned (vector unsigned int x, vector unsigned int y)
+{
+  return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vslw" 2 } } */
+/* { dg-final { scan-assembler-times "vsrw" 2 } } */
+/* { dg-final { scan-assembler-times "vsraw" 2 } } */
+/* { dg-final { scan-assembler-times "vrlw" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-fwrapv.c
new file mode 100644
index 0000000..3426480
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-fwrapv.c
@@ -0,0 +1,48 @@
+/* Verify that overloaded built-ins for vec_sl produce the right results.  */
+/* This test covers the shift left tests with the -fwrapv option. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -fwrapv" } */
+
+#include <altivec.h>
+
+vector signed char
+testsl_signed_char (vector signed char x, vector unsigned char y)
+{
+  return vec_sl (x, y);
+}
+
+vector unsigned char
+testsl_unsigned_char (vector unsigned char x, vector unsigned char y)
+{
+  return vec_sl (x, y);
+}
+
+vector signed short
+testsl_signed_short (vector signed short x, vector unsigned short y)
+{
+  return vec_sl (x, y);
+}
+
+vector unsigned short
+testsl_unsigned_short (vector unsigned short x, vector unsigned short y)
+{
+  return vec_sl (x, y);
+}
+
+vector signed int
+testsl_signed_int (vector signed int x, vector unsigned int y)
+{
+  return vec_sl (x, y);
+}
+
+vector unsigned int
+testsl_unsigned_int (vector unsigned int x, vector unsigned int y)
+{
+  return vec_sl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vslb" 2 } } */
+/* { dg-final { scan-assembler-times "vslh" 2 } } */
+/* { dg-final { scan-assembler-times "vslw" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c
new file mode 100644
index 0000000..b776683
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c
@@ -0,0 +1,22 @@
+/* Verify that overloaded built-ins for vec_sl produce the right results.  */
+/* This test covers the shift left tests with the -fwrapv option. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mpower8-vector -fwrapv" } */
+
+#include <altivec.h>
+
+vector signed long long
+testsl_signed_longlong (vector signed long long x, vector unsigned long long y)
+{
+  return vec_sl (x, y);
+}
+
+vector unsigned long long
+testsl_unsigned_longlong (vector unsigned long long x, vector unsigned long long y)
+{
+  return vec_sl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vsld" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong.c
new file mode 100644
index 0000000..f040486
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong.c
@@ -0,0 +1,22 @@
+/* cross section of shift tests specific for shift-left.
+ * This is a counterpart to the fold-vec-shift-left-frwapv test.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector signed long long
+testsl_signed_longlong (vector signed long long x, vector unsigned long long y)
+{
+  return vec_sl (x, y);
+}
+
+vector unsigned long long
+testsl_unsigned_longlong (vector unsigned long long x, vector unsigned long long y)
+{
+  return vec_sl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vsld" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left.c
new file mode 100644
index 0000000..36f92b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left.c
@@ -0,0 +1,48 @@
+/* cross section of shift tests specific for shift-left.
+ * This is a counterpart to the fold-vec-shift-left-frwapv test.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed char
+testsl_signed_char (vector signed char x, vector unsigned char y)
+{
+  return vec_sl (x, y);
+}
+
+vector unsigned char
+testsl_unsigned_char (vector unsigned char x, vector unsigned char y)
+{
+  return vec_sl (x, y);
+}
+
+vector signed short
+testsl_signed_short (vector signed short x, vector unsigned short y)
+{
+  return vec_sl (x, y);
+}
+
+vector unsigned short
+testsl_unsigned_short (vector unsigned short x, vector unsigned short y)
+{
+  return vec_sl (x, y);
+}
+
+vector signed int
+testsl_signed_int (vector signed int x, vector unsigned int y)
+{
+  return vec_sl (x, y);
+}
+
+vector unsigned int
+testsl_unsigned_int (vector unsigned int x, vector unsigned int y)
+{
+  return vec_sl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vslb" 2 } } */
+/* { dg-final { scan-assembler-times "vslh" 2 } } */
+/* { dg-final { scan-assembler-times "vslw" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c
new file mode 100644
index 0000000..97b82cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c
@@ -0,0 +1,63 @@
+/* Verify that overloaded built-ins for vec_sl with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector signed long long
+testsl_signed (vector signed long long x, vector unsigned long long y)
+{
+  return vec_sl (x, y);
+}
+
+vector unsigned long long
+testsl_unsigned (vector unsigned long long x, vector unsigned long long y)
+{
+  return vec_sl (x, y);
+}
+
+vector signed long long
+testsr_signed (vector signed long long x, vector unsigned long long y)
+{
+  return vec_sr (x, y);
+}
+
+vector unsigned long long
+testsr_unsigned (vector unsigned long long x, vector unsigned long long y)
+{
+  return vec_sr (x, y);
+}
+
+vector signed long long
+testsra_signed (vector signed long long x, vector unsigned long long y)
+{
+  return vec_sra (x, y);
+}
+
+/* watch for PR 79544 here (vsrd / vsrad issue) */
+vector unsigned long long
+testsra_unsigned (vector unsigned long long x, vector unsigned long long y)
+{
+  return vec_sra (x, y);
+}
+
+vector signed long long
+testrl_signed (vector signed long long x, vector unsigned long long y)
+{
+  return vec_rl (x, y);
+}
+
+vector unsigned long long
+testrl_unsigned (vector unsigned long long x, vector unsigned long long y)
+{
+  return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vsld" 2 } } */
+/* { dg-final { scan-assembler-times "vsrd" 2 } } */
+/* { dg-final { scan-assembler-times "vsrad" 2 } } */
+/* { dg-final { scan-assembler-times "vrld" 2 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-short.c
new file mode 100644
index 0000000..4ca7c18
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-short.c
@@ -0,0 +1,61 @@
+/* Verify that overloaded built-ins for vec_sl with short
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed short
+testsl_signed (vector signed short x, vector unsigned short y)
+{
+  return vec_sl (x, y);
+}
+
+vector unsigned short
+testsl_unsigned (vector unsigned short x, vector unsigned short y)
+{
+  return vec_sl (x, y);
+}
+
+vector signed short
+testsr_signed (vector signed short x, vector unsigned short y)
+{
+  return vec_sr (x, y);
+}
+
+vector unsigned short
+testsr_unsigned (vector unsigned short x, vector unsigned short y)
+{
+  return vec_sr (x, y);
+}
+
+vector signed short
+testsra_signed (vector signed short x, vector unsigned short y)
+{
+  return vec_sra (x, y);
+}
+
+vector unsigned short
+testsra_unsigned (vector unsigned short x, vector unsigned short y)
+{
+  return vec_sra (x, y);
+}
+
+vector signed short
+testrl_signed (vector signed short x, vector unsigned short y)
+{
+  return vec_rl (x, y);
+}
+
+vector unsigned short
+testrl_unsigned (vector unsigned short x, vector unsigned short y)
+{
+  return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vslh" 2 } } */
+/* { dg-final { scan-assembler-times "vsrh" 2 } } */
+/* { dg-final { scan-assembler-times "vsrah" 2 } } */
+/* { dg-final { scan-assembler-times "vrlh" 2 } } */

Re: [PATCH, rs6000] (v3) Fold vector shifts in GIMPLE

[Segher Boessenkool]

Hi Will,

On Tue, Jun 13, 2017 at 02:44:45PM -0500, Will Schmidt wrote:
> I sniff-tested the latest changes on Power8, with good results.  Full
> regtest running.  OK for trunk?

This looks good to me, if Richard is happy with it now.  Some very minor
things and it is good to go:

> 	2017-06-13  Will Schmidt  <will_schmidt@vnet.ibm.com>
> 
> 	* config/rs6000/rs6000.c: Add include of ssa-propagate.h for
> 	update_call_from_tree().
> 	(rs6000_gimple_fold_builtin): Add handling
> 	for early expansion of vector shifts (sl,sr,sra,rl).

Funny line break there.

> +  /* Flavors of vector shift right algebraic.
> +   * vec_sra{b,h,w} -> vsra{b,h,w}.  */

No leading * in comments please (more of those below).

> +	/* convert arg0 to unsigned.  */

Full sentences are capitalized.


Segher

Re: [PATCH, rs6000] (v3) Fold vector shifts in GIMPLE

[Richard Biener]

On Thu, Jun 15, 2017 at 7:53 PM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> Hi Will,
>
> On Tue, Jun 13, 2017 at 02:44:45PM -0500, Will Schmidt wrote:
>> I sniff-tested the latest changes on Power8, with good results.  Full
>> regtest running.  OK for trunk?
>
> This looks good to me, if Richard is happy with it now.  Some very minor
> things and it is good to go:

Yes, looks good to me.

Richard.

>>       2017-06-13  Will Schmidt  <will_schmidt@vnet.ibm.com>
>>
>>       * config/rs6000/rs6000.c: Add include of ssa-propagate.h for
>>       update_call_from_tree().
>>       (rs6000_gimple_fold_builtin): Add handling
>>       for early expansion of vector shifts (sl,sr,sra,rl).
>
> Funny line break there.
>
>> +  /* Flavors of vector shift right algebraic.
>> +   * vec_sra{b,h,w} -> vsra{b,h,w}.  */
>
> No leading * in comments please (more of those below).
>
>> +     /* convert arg0 to unsigned.  */
>
> Full sentences are capitalized.
>
>
> Segher