public inbox for gcc-patches@gcc.gnu.org
 help / color / mirror / Atom feed
From: Richard Biener <richard.guenther@gmail.com>
To: Hongyu Wang <hongyu.wang@intel.com>
Cc: gcc-patches@gcc.gnu.org, jakub@redhat.com, hongtao.liu@intel.com,
	 hubicka@ucw.cz
Subject: Re: [PATCH 00/13] [RFC] Support Intel APX EGPR
Date: Thu, 31 Aug 2023 11:19:00 +0200	[thread overview]
Message-ID: <CAFiYyc3eJgPNTL+XmE-MkawHVP1UCwn6ZB0g4x3e8M0QZcBPxw@mail.gmail.com> (raw)
In-Reply-To: <20230831082024.314097-1-hongyu.wang@intel.com>

On Thu, Aug 31, 2023 at 10:22 AM Hongyu Wang via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Intel Advanced performance extension (APX) has been released in [1].
> It contains several extensions such as extended 16 general purpose registers
> (EGPRs), push2/pop2, new data destination (NDD), conditional compare
> (CCMP/CTEST) combined with suppress flags write version of common instructions
> (NF). This RFC focused on EGPR implementation in GCC.
>
> APX introduces a REX2 prefix to help represent EGPR for several legacy/SSE
> instructions. For the remaining ones, it promotes some of them using evex
> prefix for EGPR.  The main issue in APX is that not all legacy/sse/vex
> instructions support EGPR. For example, instructions in legacy opcode map2/3
> cannot use REX2 prefix since there is only 1bit in REX2 to indicate map0/1
> instructions, e.g., pinsrd. Also, for most vector extensions, EGPR is supported
> in their evex forms but not vex forms, which means the mnemonics with no evex
> forms also cannot use EGPR, e.g., vphaddw.
>
> Such limitation brings some challenge with current GCC infrastructure.
> Generally, we use constraints to guide register allocation behavior. For
> register operand, it is easy to add a new constraint to certain insn and limit
> it to legacy or REX registers. But for memory operand, if we only use
> constraint to limit base/index register choice, reload has no backoff when
> process_address allocates any egprs to base/index reg, and then any post-reload
> pass would get ICE from the constraint.

How realistic would it be to simply disable instructions not supporting EGPR?
I hope there are alternatives that would be available in actual APX
implementations?
Otherwise this design limitation doesn't shed a very positive light on
the designers ...

How sure are we actual implementations with APX will appear (just
remembering SSE5...)?
I'm quite sure it's not going to be 2024 so would it be realistic to
post-pone APX work
to next stage1, targeting GCC 15 only?

> Here is what we did to address the issue:
>
> Middle-end:
> -       Add rtx_insn parameter to base_reg_class, reuse the
> MODE_CODE_BASE_REG_CLASS macro with rtx_insn parameter.
> -       Add index_reg_class like base_reg_class, calls new INSN_INDEX_REG_CLASS
> macro with rtx_insn parameter.
> -       In process_address_1, add rtx_insn parameter to call sites of
> base_reg_class, replace usage of INDEX_REG_CLASS to index_reg_class with
> rtx_insn parameter.
>
> Back-end:
> -       Extend GENERAL_REG_CLASS, INDEX_REG_CLASS and their supersets with
> corresponding regno checks for EGPRs.
> -       Add GENERAL_GPR16/INDEX_GPR16 class for old 16 GPRs.
> -       Whole component is controlled under -mapxf/TARGET_APX_EGPR. If it is
> not enabled, clear r16-r31 in accessible_reg_set.
> -       New register_constraint “h” and memory_constraint “Bt” that disallows
> EGPRs in operand.
> -       New asm_gpr32 flag option to enable/disable gpr32 for inline asm,
>   disabled by default.
> -       If asm_gpr32 is disabled, replace constraints “r” to “h”, and
> “m/memory” to “Bt”.
> -       Extra insn attribute gpr32, value 0 indicates the alternative cannot
> use EGPRs.
> -       Add target functions for base_reg_class and index_reg_class, calls a
> helper function to verify if insn can use EGPR in its memory_operand.
> -       In the helper function, the verify process works as follow:
>     1. Returns true if APX_EGPR disabled or insn is null.
>     2. If the insn is inline asm, returns asm_gpr32 flag.
>     3. Returns false for unrecognizable insn.
>     4. Save recog_data and which_alternative, extract the insn, and restore them
>     before return.
>     5. Loop through all enabled alternatives, if one of the enabled alternatives
>     have attr_gpr32 0, returns false, otherwise returns true.
> -       For insn alternatives that cannot use gpr32 in register_operand, use h
> constraint instead of r.
> -       For insn alternatives that cannot use gpr32 in memory operand, use Bt
> constraint instead of m, and set corresponding attr_gpr32 to 0.
> -       Split output template with %v if the sse version of mnemonic cannot use
> gpr32.
> -       For insn alternatives that cannot use gpr32 in memory operand, classify
> the isa attribute and split alternatives to noavx, avx_noavx512f and etc., so
> the helper function can properly loop through the available enabled mask.
>
> Specifically for inline asm, we currently just map “r/m/memory” constraints as
> an example. Eventually we will support entire mapping of all common constraints
> if the mapping method was accepted.
>
> Also, for vex instructions, currently we assume egpr was supported if they have
> evex counterpart, since any APX enabled machine will have AVX10 support for all
> the evex encodings. We just disabled those mnemonics that doesn’t support EGPR.
> So EGPR will be allowed under -mavx2 -mapxf for many vex mnemonics.
>
> We haven’t disabled EGPR for 3DNOW/XOP/LWP/FMA4/TBM instructions, as they will
> be co-operated with -mapxf. We can disable EGPR for them if AMD guys requires.

I think most of these are retired by now, so it's unlikely an
implementation providing
these and also APX will appear.

I have no comments on the implementation other than having instructions
that do not support the upper GPRs is quite ugly.  I don't know of any other
target with this kind of restriction, if there is any we could see how it deals
with such situation.

Richard.

> For testing, currently we tested GCC testsuite and spec2017 with -maxf+sde
> simulater and no more errors. Also, we inverted the register allocation order
> to force r31 to be allocated first, and no more error except those AMD only
> instructions. We will conduct further tests like changing all do-compile to
> do-assemble and add more to gcc/testsuite in the future.
>
> The RFC intends to describe our approach for APX implementation for EGPR
> component. It may still have potential issues or bugs and requires futher
> optimization. Any comments are very appreciated.
>
> [1]. https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html.
>
> Hongyu Wang (2):
>   [APX EGPR] middle-end: Add index_reg_class with insn argument.
>   [APX EGPR] Handle GPR16 only vector move insns
>
> Kong Lingling (11):
>   [APX EGPR] middle-end: Add insn argument to base_reg_class
>   [APX_EGPR] Initial support for APX_F
>   [APX EGPR] Add 16 new integer general purpose registers
>   [APX EGPR] Add register and memory constraints that disallow EGPR
>   [APX EGPR] Map reg/mem constraints in inline asm to non-EGPR
>     constraint.
>   [APX EGPR] Add backend hook for base_reg_class/index_reg_class.
>   [APX EGPR] Handle legacy insn that only support GPR16 (1/5)
>   [APX EGPR] Handle legacy insns that only support GPR16 (2/5)
>   [APX EGPR] Handle legacy insns that only support GPR16 (3/5)
>   [APX_EGPR] Handle legacy insns that only support GPR16 (4/5)
>   [APX EGPR] Handle vex insns that only support GPR16 (5/5)
>
>  gcc/addresses.h                               |  25 +-
>  gcc/common/config/i386/cpuinfo.h              |  12 +-
>  gcc/common/config/i386/i386-common.cc         |  17 +
>  gcc/common/config/i386/i386-cpuinfo.h         |   1 +
>  gcc/common/config/i386/i386-isas.h            |   1 +
>  gcc/config/avr/avr.h                          |   5 +-
>  gcc/config/gcn/gcn.h                          |   4 +-
>  gcc/config/i386/constraints.md                |  26 +-
>  gcc/config/i386/cpuid.h                       |   1 +
>  gcc/config/i386/i386-isa.def                  |   1 +
>  gcc/config/i386/i386-options.cc               |  15 +
>  gcc/config/i386/i386-opts.h                   |   8 +
>  gcc/config/i386/i386-protos.h                 |   9 +
>  gcc/config/i386/i386.cc                       | 253 +++++-
>  gcc/config/i386/i386.h                        |  69 +-
>  gcc/config/i386/i386.md                       | 144 ++-
>  gcc/config/i386/i386.opt                      |  30 +
>  gcc/config/i386/mmx.md                        | 170 ++--
>  gcc/config/i386/sse.md                        | 859 ++++++++++++------
>  gcc/config/rl78/rl78.h                        |   6 +-
>  gcc/doc/invoke.texi                           |  11 +-
>  gcc/doc/tm.texi                               |  17 +-
>  gcc/doc/tm.texi.in                            |  17 +-
>  gcc/lra-constraints.cc                        |  32 +-
>  gcc/reload.cc                                 |  34 +-
>  gcc/reload1.cc                                |   2 +-
>  gcc/testsuite/gcc.target/i386/apx-1.c         |   8 +
>  .../gcc.target/i386/apx-egprs-names.c         |  17 +
>  .../gcc.target/i386/apx-inline-gpr-norex2.c   | 108 +++
>  .../gcc.target/i386/apx-interrupt-1.c         | 102 +++
>  .../i386/apx-legacy-insn-check-norex2-asm.c   |   5 +
>  .../i386/apx-legacy-insn-check-norex2.c       | 181 ++++
>  .../gcc.target/i386/apx-spill_to_egprs-1.c    |  25 +
>  gcc/testsuite/lib/target-supports.exp         |  10 +
>  34 files changed, 1747 insertions(+), 478 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/i386/apx-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/apx-egprs-names.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/apx-inline-gpr-norex2.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/apx-interrupt-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/apx-spill_to_egprs-1.c
>
> --
> 2.31.1
>

  parent reply	other threads:[~2023-08-31  9:20 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-31  8:20 Hongyu Wang
2023-08-31  8:20 ` [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class Hongyu Wang
2023-08-31 10:15   ` Uros Bizjak
2023-09-01  9:07     ` Hongyu Wang
2023-09-06 19:43       ` Vladimir Makarov
2023-09-07  6:23         ` Uros Bizjak
2023-09-07 12:13           ` Vladimir Makarov
2023-09-08 17:03   ` Vladimir Makarov
2023-09-10  4:49     ` Hongyu Wang
2023-09-14 12:09       ` Vladimir Makarov
2023-08-31  8:20 ` [PATCH 02/13] [APX EGPR] middle-end: Add index_reg_class with insn argument Hongyu Wang
2023-08-31  8:20 ` [PATCH 03/13] [APX_EGPR] Initial support for APX_F Hongyu Wang
2023-08-31  8:20 ` [PATCH 04/13] [APX EGPR] Add 16 new integer general purpose registers Hongyu Wang
2023-08-31  8:20 ` [PATCH 05/13] [APX EGPR] Add register and memory constraints that disallow EGPR Hongyu Wang
2023-08-31  8:20 ` [PATCH 06/13] [APX EGPR] Map reg/mem constraints in inline asm to non-EGPR constraint Hongyu Wang
2023-08-31  9:17   ` Jakub Jelinek
2023-08-31 10:00     ` Uros Bizjak
2023-09-01  9:04       ` Hongyu Wang
2023-09-01  9:38         ` Uros Bizjak
2023-09-01 10:35           ` Hongtao Liu
2023-09-01 11:27             ` Uros Bizjak
2023-09-04  0:28               ` Hongtao Liu
2023-09-04  8:57                 ` Uros Bizjak
2023-09-04  9:10                   ` Hongtao Liu
2023-09-01 11:03       ` Richard Sandiford
2023-09-04  1:03         ` Hongtao Liu
2023-09-01  9:04     ` Hongyu Wang
2023-08-31  8:20 ` [PATCH 07/13] [APX EGPR] Add backend hook for base_reg_class/index_reg_class Hongyu Wang
2023-08-31  8:20 ` [PATCH 08/13] [APX EGPR] Handle GPR16 only vector move insns Hongyu Wang
2023-08-31  9:43   ` Jakub Jelinek
2023-09-01  9:07     ` Hongyu Wang
2023-09-01  9:20       ` Jakub Jelinek
2023-09-01 11:34         ` Hongyu Wang
2023-09-01 11:41           ` Jakub Jelinek
2023-08-31  8:20 ` [PATCH 09/13] [APX EGPR] Handle legacy insn that only support GPR16 (1/5) Hongyu Wang
2023-08-31 10:06   ` Uros Bizjak
2023-08-31  8:20 ` [PATCH 10/13] [APX EGPR] Handle legacy insns that only support GPR16 (2/5) Hongyu Wang
2023-08-31  8:20 ` [PATCH 11/13] [APX EGPR] Handle legacy insns that only support GPR16 (3/5) Hongyu Wang
2023-08-31  9:26   ` Richard Biener
2023-08-31  9:28     ` Richard Biener
2023-09-01  9:03       ` Hongyu Wang
2023-09-01 10:38       ` Hongtao Liu
2023-08-31  9:31     ` Jakub Jelinek
2023-08-31  8:20 ` [PATCH 12/13] [APX_EGPR] Handle legacy insns that only support GPR16 (4/5) Hongyu Wang
2023-08-31  8:20 ` [PATCH 13/13] [APX EGPR] Handle vex insns that only support GPR16 (5/5) Hongyu Wang
2023-08-31  9:19 ` Richard Biener [this message]
2023-09-01  8:55   ` [PATCH 00/13] [RFC] Support Intel APX EGPR Hongyu Wang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAFiYyc3eJgPNTL+XmE-MkawHVP1UCwn6ZB0g4x3e8M0QZcBPxw@mail.gmail.com \
    --to=richard.guenther@gmail.com \
    --cc=gcc-patches@gcc.gnu.org \
    --cc=hongtao.liu@intel.com \
    --cc=hongyu.wang@intel.com \
    --cc=hubicka@ucw.cz \
    --cc=jakub@redhat.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).