From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by sourceware.org (Postfix) with ESMTPS id 0BD023858D37 for ; Thu, 20 Apr 2023 11:10:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0BD023858D37 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-lj1-x233.google.com with SMTP id y24so2334302ljm.6 for ; Thu, 20 Apr 2023 04:10:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681989006; x=1684581006; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=Vru8r+nZm95g/377ybWDJ8XDmUlIkK5V1jSlGWNfwAU=; b=TiCn/o/9c1RVZ79oSKH9ZdZMUX6t4GDIbHh153lTH4TiFQ6FIAntGTvbWdBTjcVPC1 wrOv1s1tZFRXAYepPJDh6P+msMA7ffDpsY6ancMN5I31pVIyjXfSqJ105wB3vm3y+k1+ ajnUgfm8wFrSg99aPfpJqRD8CyNYxZB1eN/RZ2cg3FR6U9GSxYNbmcbCVHyjkbopM0l0 zIbqMhhbUIQty3UbnsJXnfqogH7FwG1rMD8gMV2w5avV04fiEYVfiJQjTtVJXZ4HUdNL RL0RJZIPW4Yku8yWSAi9/D3JlTK7iDegIWF/qDuVBZEdpNNma/rfhC/nftKpCs8mjuFm Dt1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681989006; x=1684581006; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vru8r+nZm95g/377ybWDJ8XDmUlIkK5V1jSlGWNfwAU=; b=c5pUhKBAz7GZPyq7vImR9ZjLe+xpTByxh5HWP8gtSmu3zXaM2ixx5jyVRLVzTlqLCG hniXHiwiOcXy7o5uYvuEeCFGjhCSO+eJHb5dK+0vjSgR41nv16YLHWv4nDFHGxB7zNes BgchZjn19RE8D1A+Ixhasbu/VPYY0Uv0TwEF/GCuJ1N5/1FZ8+OPjTYu5YI0RKAfsf9M eJuVTDZ8f0ppRqpcSTZlyU2XD8GgC+tEDdnQ6+O3/Llw8BL3ZkQUUqi9ZPpT7eR9vPb/ /aDq7x+9nB34CAgh5E8/x+NgGZc2l4yQT+0AQ4AeVpps3k50hnH1BQ8RA4JsZTz4wQzE oE+Q== X-Gm-Message-State: AAQBX9cV8AZWL23OmAvIFGM8Z9zPKXe2cUrcwEAq8ZkBeNfwpvdwyDPY h8CXRH/YroJBYDGzDB1RUc1CpMM2d84UZ5E/dU8= X-Google-Smtp-Source: AKy350a4qFCCStnhm7o2rsg+/gcz/SeldZ4SIoxYZt4dlYcCyLjkDXFfFFMpyIr+yVYhk/t5cFpepfkH3ivp0ZbJAnM= X-Received: by 2002:a2e:9c4e:0:b0:2a8:bc46:6ba1 with SMTP id t14-20020a2e9c4e000000b002a8bc466ba1mr258709ljj.3.1681989006274; Thu, 20 Apr 2023 04:10:06 -0700 (PDT) MIME-Version: 1.0 References: <20230419163634.1030144-1-juzhe.zhong@rivai.ai> <20230419163634.1030144-2-juzhe.zhong@rivai.ai> In-Reply-To: <20230419163634.1030144-2-juzhe.zhong@rivai.ai> From: Richard Biener Date: Thu, 20 Apr 2023 13:08:58 +0200 Message-ID: Subject: Re: [PATCH 1/3] RISC-V: Add auto-vectorization compile option for RVV To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Apr 19, 2023 at 6:38=E2=80=AFPM wrote: > > From: Ju-Zhe Zhong > > This patch is adding 2 compile option for RVV auto-vectorization. > 1. -param=3Driscv-autovec-preference=3D > This option is to specify the auto-vectorization approach for RVV. > Currently, we only support scalable and fixed-vlmax. > > - scalable means VLA auto-vectorization. The vector-length to compile= r is > unknown and runtime invariant. Such approach can allow us compile t= he code > run on any vector-length RVV CPU. > > - fixed-vlmax means the compile known the RVV CPU vector-length, comp= ile option > in fixed-length VLS auto-vectorization. Meaning if we specify vecto= r-length=3D512. > The execution file can only run on vector-length =3D 512 RVV CPU. > > - TODO: we may need to support min-length VLS auto-vectorization, mea= ns the execution > file can run on larger length RVV CPU. Just as a generic comment - if the option should be exposed to users rather than just used for testsuite or development purposes it should eventually become a -mautovec-preference=3D flag (no need to prefix with riscv). > gcc/ChangeLog: > > * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum):= Add enum for auto-vectorization preference. > (enum riscv_autovec_lmul_enum): Add enum for choosing LMUL of RVV= auto-vectorization. > * config/riscv/riscv.opt: Add compile option for RVV auto-vectori= zation. > > --- > gcc/config/riscv/riscv-opts.h | 15 ++++++++++++++ > gcc/config/riscv/riscv.opt | 37 +++++++++++++++++++++++++++++++++++ > 2 files changed, 52 insertions(+) > > diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.= h > index cf0cd669be4..4207db240ea 100644 > --- a/gcc/config/riscv/riscv-opts.h > +++ b/gcc/config/riscv/riscv-opts.h > @@ -67,6 +67,21 @@ enum stack_protector_guard { > SSP_GLOBAL /* global canary */ > }; > > +/* RISC-V auto-vectorization preference. */ > +enum riscv_autovec_preference_enum { > + NO_AUTOVEC, > + RVV_SCALABLE, > + RVV_FIXED_VLMAX > +}; > + > +/* RISC-V auto-vectorization RVV LMUL. */ > +enum riscv_autovec_lmul_enum { > + RVV_M1 =3D 1, > + RVV_M2 =3D 2, > + RVV_M4 =3D 4, > + RVV_M8 =3D 8 > +}; > + > #define MASK_ZICSR (1 << 0) > #define MASK_ZIFENCEI (1 << 1) > > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index ff1dd4ddd4f..ef1bdfcfe28 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -254,3 +254,40 @@ Enum(isa_spec_class) String(20191213) Value(ISA_SPEC= _CLASS_20191213) > misa-spec=3D > Target RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) In= it(TARGET_DEFAULT_ISA_SPEC) > Set the version of RISC-V ISA spec. > + > +Enum > +Name(riscv_autovec_preference) Type(enum riscv_autovec_preference_enum) > +The RISC-V auto-vectorization preference: > + > +EnumValue > +Enum(riscv_autovec_preference) String(none) Value(NO_AUTOVEC) > + > +EnumValue > +Enum(riscv_autovec_preference) String(scalable) Value(RVV_SCALABLE) > + > +EnumValue > +Enum(riscv_autovec_preference) String(fixed-vlmax) Value(RVV_FIXED_VLMAX= ) > + > +-param=3Driscv-autovec-preference=3D > +Target RejectNegative Joined Enum(riscv_autovec_preference) Var(riscv_au= tovec_preference) Init(NO_AUTOVEC) > +-param=3Driscv-autovec-preference=3D Set the preference of= auto-vectorization in the RISC-V port. > + > +Enum > +Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum) > +The RVV possible LMUL: > + > +EnumValue > +Enum(riscv_autovec_lmul) String(m1) Value(RVV_M1) > + > +EnumValue > +Enum(riscv_autovec_lmul) String(m2) Value(RVV_M2) > + > +EnumValue > +Enum(riscv_autovec_lmul) String(m4) Value(RVV_M4) > + > +EnumValue > +Enum(riscv_autovec_lmul) String(m8) Value(RVV_M8) > + > +-param=3Driscv-autovec-lmul=3D > +Target RejectNegative Joined Enum(riscv_autovec_lmul) Var(riscv_autovec_= lmul) Init(RVV_M1) > +-param=3Driscv-autovec-lmul=3D Set the RVV LMUL of auto-vect= orization in the RISC-V port. > -- > 2.36.3 >