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References: <20230717033334.2376251-1-haochen.jiang@intel.com>
In-Reply-To: <20230717033334.2376251-1-haochen.jiang@intel.com>
From: Richard Biener
Date: Mon, 17 Jul 2023 08:40:04 +0200
Message-ID:
Subject: Re: [PATCH] [gcc-wwwdocs]gcc-13/14: Mention Intel new ISA and march support
To: Haochen Jiang
Cc: gcc-patches@gcc.gnu.org, hongtao.liu@intel.com, ubizjak@gmail.com
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On Mon, Jul 17, 2023 at 5:34=E2=80=AFAM Haochen Jiang via Gcc-patches
wrote:
>
> Hi all,
>
> This patch adds documentation to wwwdocs to mention the recent introducti=
on
> of Intel new ISA and march.
>
> Ok for trunk?
OK.
> BRs,
> Haochen
>
> ---
> htdocs/gcc-13/changes.html | 4 ++++
> htdocs/gcc-14/changes.html | 34 +++++++++++++++++++++++++++++++++-
> 2 files changed, 37 insertions(+), 1 deletion(-)
>
> diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
> index 39414e18..68e8c5cc 100644
> --- a/htdocs/gcc-13/changes.html
> +++ b/htdocs/gcc-13/changes.html
> @@ -593,6 +593,10 @@ You may also want to check out our
>
> GCC now supports the Intel CPU named Granite Rapids through
> -march=3Dgraniterapids
.
> + The switch enables the AMX-FP16, PREFETCHI ISA extensions.
> +
> + GCC now supports the Intel CPU named Granite Rapids D through
> + -march=3Dgraniterapids-d
.
> The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA exten=
sions.
>
> GCC now supports AMD CPUs based on the znver4
core
> diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
> index 3f797642..dad1ba53 100644
> --- a/htdocs/gcc-14/changes.html
> +++ b/htdocs/gcc-14/changes.html
> @@ -108,7 +108,39 @@ a work-in-progress.
>
>
>
> -
> +IA-32/x86-64
> +
> + - New ISA extension support for Intel AVX-VNNI-INT16 was added.
> + AVX-VNNI-INT16 intrinsics are available via the
-mavxvnniint=
16
> + compiler switch.
> +
> + - New ISA extension support for Intel SHA512 was added.
> + SHA512 intrinsics are available via the
-msha512
> + compiler switch.
> +
> + - New ISA extension support for Intel SM3 was added.
> + SM3 intrinsics are available via the
-msm3
> + compiler switch.
> +
> + - New ISA extension support for Intel SM4 was added.
> + SM4 intrinsics are available via the
-msm4
> + compiler switch.
> +
> + - GCC now supports the Intel CPU named Arrow Lake through
> +
-march=3Darrowlake
.
> + Based on Alder Lake, the switch further enables the AVX-IFMA,
> + AVX-VNNI-INT8, AVX-NE-CONVERT and CMPccXADD ISA extensions.
> +
> + - GCC now supports the Intel CPU named Arrow Lake S through
> +
-march=3Darrowlake-s
.
> + Based on Arrow Lake, the switch further enables the AVX-VNNI-INT16, =
SHA512,
> + SM3 and SM4 ISA extensions.
> +
> + - GCC now supports the Intel CPU named Lunar Lake through
> +
-march=3Dlunarlake
.
> + Lunar Lake is based on Arrow Lake S.
> +
> +
>
>
>
> --
> 2.31.1
>