From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 101743 invoked by alias); 25 Jul 2018 08:28:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 99685 invoked by uid 89); 25 Jul 2018 08:28:46 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.0 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=Tested X-HELO: mail-lj1-f193.google.com Received: from mail-lj1-f193.google.com (HELO mail-lj1-f193.google.com) (209.85.208.193) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 25 Jul 2018 08:28:44 +0000 Received: by mail-lj1-f193.google.com with SMTP id j19-v6so5930033ljc.7 for ; Wed, 25 Jul 2018 01:28:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=sVC7i4HvW8gE6TrdqTAZNkkPWdDEShqhx/SnFyfLtpE=; b=LMqHvAb7rt5EoyyvShLdW4M7ucCWyxAEh5YXwWC6oZe0kYZU6ubvGi6kOoFURQW9M7 OF5VHbUZBE+m6f9w472stY1Aa50XLYU/7+yo0HNPaOi12npowFtBMYZ0kpgwEa08wXlO cKOYKzNyQ8EV3XTdDeWtdeKtTVlicUPzadfqWJLtd5ec6ksC0cXDZs8YoOJHxmCaajfQ iw9aN6ztQXSVgVqQVXGP07m0Di0M53/XnfQtiasYkM1ZAp/++MLWFFFbWcMLeFgtrMTC L6MqD2JrcM+qgeG9QuxI/cbjDsMIw2XZVh8XS/9D/dpVfsQS47Ux+qbip9BXVDr5vF7A /5Xg== MIME-Version: 1.0 References: <402e00c62fa533333b1e1dd69f468f7f4e43939b.1532449714.git.segher@kernel.crashing.org> In-Reply-To: <402e00c62fa533333b1e1dd69f468f7f4e43939b.1532449714.git.segher@kernel.crashing.org> From: Richard Biener Date: Wed, 25 Jul 2018 08:28:00 -0000 Message-ID: Subject: Re: [PATCH] combine: Allow combining two insns to two insns To: Segher Boessenkool Cc: GCC Patches Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2018-07/txt/msg01460.txt.bz2 On Tue, Jul 24, 2018 at 7:18 PM Segher Boessenkool wrote: > > This patch allows combine to combine two insns into two. This helps > in many cases, by reducing instruction path length, and also allowing > further combinations to happen. PR85160 is a typical example of code > that it can improve. > > This patch does not allow such combinations if either of the original > instructions was a simple move instruction. In those cases combining > the two instructions increases register pressure without improving the > code. With this move test register pressure does no longer increase > noticably as far as I can tell. > > (At first I also didn't allow either of the resulting insns to be a > move instruction. But that is actually a very good thing to have, as > should have been obvious). > > Tested for many months; tested on about 30 targets. > > I'll commit this later this week if there are no objections. Sounds good - but, _any_ testcase? Please! ;) Richard. > > Segher > > > 2018-07-24 Segher Boessenkool > > PR rtl-optimization/85160 > * combine.c (is_just_move): New function. > (try_combine): Allow combining two instructions into two if neither of > the original instructions was a move. > > --- > gcc/combine.c | 22 ++++++++++++++++++++-- > 1 file changed, 20 insertions(+), 2 deletions(-) > > diff --git a/gcc/combine.c b/gcc/combine.c > index cfe0f19..d64e84d 100644 > --- a/gcc/combine.c > +++ b/gcc/combine.c > @@ -2604,6 +2604,17 @@ can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n) > return true; > } > > +/* Return whether X is just a single set, with the source > + a general_operand. */ > +static bool > +is_just_move (rtx x) > +{ > + if (INSN_P (x)) > + x = PATTERN (x); > + > + return (GET_CODE (x) == SET && general_operand (SET_SRC (x), VOIDmode)); > +} > + > /* Try to combine the insns I0, I1 and I2 into I3. > Here I0, I1 and I2 appear earlier than I3. > I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into > @@ -2668,6 +2679,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0, > int swap_i2i3 = 0; > int split_i2i3 = 0; > int changed_i3_dest = 0; > + bool i2_was_move = false, i3_was_move = false; > > int maxreg; > rtx_insn *temp_insn; > @@ -3059,6 +3071,10 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0, > return 0; > } > > + /* Record whether i2 and i3 are trivial moves. */ > + i2_was_move = is_just_move (i2); > + i3_was_move = is_just_move (i3); > + > /* Record whether I2DEST is used in I2SRC and similarly for the other > cases. Knowing this will help in register status updating below. */ > i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); > @@ -4014,8 +4030,10 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0, > && XVECLEN (newpat, 0) == 2 > && GET_CODE (XVECEXP (newpat, 0, 0)) == SET > && GET_CODE (XVECEXP (newpat, 0, 1)) == SET > - && (i1 || set_noop_p (XVECEXP (newpat, 0, 0)) > - || set_noop_p (XVECEXP (newpat, 0, 1))) > + && (i1 > + || set_noop_p (XVECEXP (newpat, 0, 0)) > + || set_noop_p (XVECEXP (newpat, 0, 1)) > + || (!i2_was_move && !i3_was_move)) > && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT > && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART > && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT > -- > 1.8.3.1 >