From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by sourceware.org (Postfix) with ESMTPS id EFFCE3858C39 for ; Fri, 19 Nov 2021 10:22:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EFFCE3858C39 Received: by mail-ed1-x52b.google.com with SMTP id x15so40714065edv.1 for ; Fri, 19 Nov 2021 02:22:08 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=1soUxKBEhLrShuUWBTetTAttqz9oYaQz/KvrSmRcTtc=; b=u8UPGNB1qcPoz9eq0alMPUDziCx+LkwoOZbK2gLliCGFr5fp5oBlhZdbDUwBiCYnUk PQuA0nXOQhGeIEwrbRzGVn6+kp//2D/oKpR9SQWg7+Ph5z8tk4GbwogEaRK8Z0ghcWEG n5wcJ9GyfIPk5ILYdtMtoXEsS9u0OxVf8AS6JiCS/cnwNxPszcJuG0kyoFqNZDtsoz3A Ax5mFZRm6D5wvCAsjYR8AxFTDVWzg3L9AzRqFesqOZwGh6cPw151drxAPbdTpXRdij3t 5sBn88qmMuCnVCbN5DZc2pu7i8ornSTsl34Df88EQSDPgtBHz2+vj3MzBJvrstEcpsfA FYtg== X-Gm-Message-State: AOAM530grWEuG1is2fjfsw587ecc4yQKZTAiTOpQbhctOIeJIBY3obeK A3gX5/bFr6J1RgkKi7OG7HAP3f5Pgwdv9Ee0jVl3rl2n X-Google-Smtp-Source: ABdhPJxSiWCZ+XjKLuvQ+pdj5jiTLBzQIARE3UjoOQ/bPgNAjYIGj1pYyj19dqJNwfpbq1Wrsyaq2M818Cb2nADwXPw= X-Received: by 2002:a17:906:388c:: with SMTP id q12mr6287467ejd.281.1637317328079; Fri, 19 Nov 2021 02:22:08 -0800 (PST) MIME-Version: 1.0 References: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> <20211111141020.2738001-2-philipp.tomsich@vrull.eu> In-Reply-To: From: Richard Biener Date: Fri, 19 Nov 2021 11:21:57 +0100 Message-ID: Subject: Re: [PATCH v1 1/8] bswap: synthesize HImode bswap from SImode or DImode To: Philipp Tomsich Cc: GCC Patches , Jim Wilson , Kito Cheng Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 Nov 2021 10:22:10 -0000 On Fri, Nov 19, 2021 at 11:20 AM Richard Biener wrote: > > On Thu, Nov 11, 2021 at 3:13 PM Philipp Tomsich > wrote: > > > > The RISC-V Zbb extension adds an XLEN (i.e. SImode for rv32, DImode > > for rv64) bswap instruction (rev8). While, with the current master, > > SImode is synthesized correctly from DImode, HImode is not. > > > > This change adds an appropriate expansion for a HImode bswap, if a > > wider bswap is available. > > > > Without this change, the following rv64gc_zbb code is generated for > > __builtin_bswap16(): > > slliw a5,a0,8 > > zext.h a0,a0 > > srliw a0,a0,8 > > or a0,a5,a0 > > sext.h a0,a0 // this is a 16bit sign-extension following > > // the byteswap (e.g. on a 'short' function > > // return). > > > > After this change, a bswap (rev8) is used and any extensions are > > combined into the shift-right: > > rev8 a0,a0 > > srai a0,a0,48 // the sign-extension is combined into the > > // shift; a srli is emitted otherwise... > > > > gcc/ChangeLog: > > > > * optabs.c (expand_unop): support expanding a HImode bswap > > using SImode or DImode, followed by a shift. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/zbb-bswap.c: New test. > > > > Signed-off-by: Philipp Tomsich > > --- > > > > gcc/optabs.c | 6 ++++++ > > gcc/testsuite/gcc.target/riscv/zbb-bswap.c | 22 ++++++++++++++++++++++ > > 2 files changed, 28 insertions(+) > > create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-bswap.c > > > > diff --git a/gcc/optabs.c b/gcc/optabs.c > > index 019bbb62882..7a3ffbe4525 100644 > > --- a/gcc/optabs.c > > +++ b/gcc/optabs.c > > @@ -3307,6 +3307,12 @@ expand_unop (machine_mode mode, optab unoptab, rtx op0, rtx target, > > return temp; > > } > > > > + /* If we are missing a HImode BSWAP, but have one for SImode or > > + DImode, use a BSWAP followed by a SHIFT. */ > > + temp = widen_bswap (as_a (mode), op0, target); > > + if (temp) > > + return temp; > > + > > I think it would be more natural to temporarily terminate the HImode case here > and re-open it inside the following > > if (is_a (mode, &int_mode)) > { > temp = widen_bswap (int_mode, op0, target); > if (temp) > return temp; > > here to handle the ashl/lshr/ior fallback. But as Kito says, code generation for more targets would need to be looked at. Richard. > Richard. > > > last = get_last_insn (); > > > > temp1 = expand_binop (mode, ashl_optab, op0, > > diff --git a/gcc/testsuite/gcc.target/riscv/zbb-bswap.c b/gcc/testsuite/gcc.target/riscv/zbb-bswap.c > > new file mode 100644 > > index 00000000000..6ee27d9f47a > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/zbb-bswap.c > > @@ -0,0 +1,22 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */ > > + > > +unsigned long > > +func64 (unsigned long i) > > +{ > > + return __builtin_bswap64(i); > > +} > > + > > +unsigned int > > +func32 (unsigned int i) > > +{ > > + return __builtin_bswap32(i); > > +} > > + > > +unsigned short > > +func16 (unsigned short i) > > +{ > > + return __builtin_bswap16(i); > > +} > > + > > +/* { dg-final { scan-assembler-times "rev8" 3 } } */ > > -- > > 2.32.0 > >