From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 60539 invoked by alias); 20 Oct 2015 17:14:26 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 60508 invoked by uid 89); 20 Oct 2015 17:14:22 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lf0-f45.google.com Received: from mail-lf0-f45.google.com (HELO mail-lf0-f45.google.com) (209.85.215.45) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 20 Oct 2015 17:14:21 +0000 Received: by lffy185 with SMTP id y185so9212125lff.2 for ; Tue, 20 Oct 2015 10:14:18 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.25.22.149 with SMTP id 21mr1686439lfw.8.1445361257938; Tue, 20 Oct 2015 10:14:17 -0700 (PDT) Received: by 10.25.165.142 with HTTP; Tue, 20 Oct 2015 10:14:17 -0700 (PDT) In-Reply-To: <56266B27.3040709@arm.com> References: <5620F47B.9010107@arm.com> <56266B27.3040709@arm.com> Date: Tue, 20 Oct 2015 17:15:00 -0000 Message-ID: Subject: Re: [PATCH][AArch64] Add support for 64-bit vector-mode ldp/stp From: Marcus Shawcroft To: Kyrill Tkachov Cc: GCC Patches , Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2015-10/txt/msg01927.txt.bz2 On 20 October 2015 at 17:26, Kyrill Tkachov wrote: > Hi Marcus, > > On 20/10/15 17:05, Marcus Shawcroft wrote: >> >> On 16 October 2015 at 13:58, Kyrill Tkachov >> wrote: >>> >>> Hi all, >>> >>> We already support load/store-pair operations on the D-registers when >>> they >>> contain an FP value, but the peepholes/sched-fusion machinery that >>> do all the hard work currently ignore 64-bit vector modes. >>> >>> This patch adds support for fusing loads/stores of 64-bit vector operands >>> into ldp and stp instructions. >>> I've seen this trigger a few times in SPEC2006. Not too many times, but >>> the >>> times it did trigger the code seemed objectively better >>> i.e. long sequences of ldr and str instructions essentially halved in >>> size. >>> >>> Bootstrapped and tested on aarch64-none-linux-gnu. >>> >>> Ok for trunk? >>> >>> Thanks, >>> Kyrill >>> >>> 2015-10-16 Kyrylo Tkachov >>> >>> * config/aarch64/aarch64.c (aarch64_mode_valid_for_sched_fusion_p): >> >> We have several different flavours of fusion in the backend, this one >> is specifically load/stores, perhaps making that clear in the name of >> this predicate will avoid confusion further down the line? > > Thanks for the review, > > This particular type of fusion is called sched_fusion in various > places in the compiler and its implementation in aarch64 is only for > load/store merging (indeed, the only usage of sched_fusion currently > is to merge loads/stores in arm and aarch64). > > So, I think that sched_fusion in the name already conveys the information > that it's the ldp/stp one rather than macro fusion. In fact, there is a > macro fusion of ADRP and an LDR instruction, > so having sched_fusion in the name is actually a better differentiator than > mentioning loads/stores as both types of fusion deal with loads in some way. > > Is it ok to keep the name as is? Thanks for the justification, patch is OK to commit /Marcus