From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 11553 invoked by alias); 19 May 2014 10:44:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 11542 invoked by uid 89); 19 May 2014 10:44:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-vc0-f177.google.com Received: from mail-vc0-f177.google.com (HELO mail-vc0-f177.google.com) (209.85.220.177) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 19 May 2014 10:44:35 +0000 Received: by mail-vc0-f177.google.com with SMTP id if17so9174795vcb.36 for ; Mon, 19 May 2014 03:44:33 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.58.201.5 with SMTP id jw5mr30072776vec.6.1400496273057; Mon, 19 May 2014 03:44:33 -0700 (PDT) Received: by 10.52.78.194 with HTTP; Mon, 19 May 2014 03:44:32 -0700 (PDT) In-Reply-To: <536bc1d0.a2a1440a.3499.ffffeb33SMTPIN_ADDED_BROKEN@mx.google.com> References: <536bc1d0.a2a1440a.3499.ffffeb33SMTPIN_ADDED_BROKEN@mx.google.com> Date: Mon, 19 May 2014 10:44:00 -0000 Message-ID: Subject: Re: [PATCH, AArch64] Fix macro in vdup_lane_2 test case From: Marcus Shawcroft To: Ian Bolton Cc: gcc-patches Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2014-05/txt/msg01471.txt.bz2 On 8 May 2014 18:41, Ian Bolton wrote: > gcc/testsuite > * gcc.target/aarch64/vdup_lane_2.c (force_simd): Emit an > actual instruction to move into the allocated register. This macro is attempting to force a value to a particular class of register, we don't need or want the mov instruction at all. Isn't something like this sufficient: #define force_simd(V1) asm volatile ("" \ : "+w"(V1) \ : \ : /* No clobbers */) ? /Marcus