Re: [PATCH][rtlanal.c][BE][1/2] Fix vector load/stores to not use ld1/st1

[Marcus Shawcroft <marcus.shawcroft@gmail.com>]

On 14 January 2015 at 07:35, Jeff Law <law@redhat.com> wrote:
> On 01/13/15 11:55, Eric Botcazou wrote:
>>
>>
>>> (1) we have a non-paradoxical subreg;
>>> (2) both (reg:ymode xregno) and (reg:xmode xregno) occupy full
>>>      hard registers (no padding or unused upper bits);
>>> (3) (reg:ymode xregno) and (reg:xmode xregno) store the same number
>>>      of bytes (X) in each constituent hard register;
>>> (4) the offset is a multiple of X, i.e. the data we're accessing
>>>      is aligned to a register boundary; and
>>> (5) endianness is regular (no differences between words and bytes,
>>>      or between registers and memory)
>>
>>
>> OK, that's a nice translation of the new code. :-)
>>
>> It seems to me that the patch wants to extend the support of generic
>> subregs
>> to modes whose sizes are not multiple of each other, which is a
>> requirement of
>> the existing code, but does that in a very specific case for the sake of
>> the
>> ARM port without saying where all the above restrictions come from.
>
> Basically we're lifting the restriction that the the sizes are multiples of
> each other.  The requirements above are the set where we know it will work.
> They are target independent, but happen to match what the ARM needs.
>
> The certainly do short circuit the meat of the function, that's the whole
> point, there's this set of conditions under which we know this will work and
> when they hold, we bypass.
>
> Now one could argue that instead of bypassing we should put the code to
> handle this situation further down.  I'd be leery of doing that just from a
> complexity standpoint.  But one could also argue that short circuiting like
> the patch does adds complexity as well and may be a bit kludgy.
>
> Maybe the way forward here is for someone to try and integrate this support
> in the main part of the code and see how it looks.  Then we can pick one.
>
> The downside is since this probably isn't a regression that work would need
> to happen quickly to make it into gcc-5.
>
> Which leads to another option, get the release managers to sign off on the
> kludge after gcc-5 branches and only install the kludge on the gcc-5 branch
> and insisting the other solution go in for gcc-6 and beyond.  Not sure if
> they'd do that, but it's a discussion that could happen.

This issue is currently gating a number of patches that get big endian
working on aarch64 (all of which are on the list), it would be good if
we could get this addressed in some form in gcc-5 rather than put out
a second release of gcc with borked BE aarch64 support.

Cheers
/Marcus