From: Jim Wilson <jimw@sifive.com>
To: Christoph Muellner <cmuellner@gcc.gnu.org>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>,
Kito Cheng <kito.cheng@sifive.com>
Subject: Re: [PATCH 10/10] RISC-V: Provide programmatic implementation of CAS [PR 100266]
Date: Tue, 27 Apr 2021 08:17:09 -0700 [thread overview]
Message-ID: <CAFyWVaagyM3he9EgzfEkhF97=BrCjbK550__rt7AN34Xdj26Dw@mail.gmail.com> (raw)
In-Reply-To: <20210426124552.3316789-11-cmuellner@gcc.gnu.org>
On Mon, Apr 26, 2021 at 5:46 AM Christoph Muellner <cmuellner@gcc.gnu.org>
wrote:
> The existing CAS implementation uses an INSN definition, which provides
> the core LR/SC sequence. Additionally to that, there is a follow-up code,
> that evaluates the results and calculates the return values.
> This has two drawbacks: a) an extension to sub-word CAS implementations
> is not possible (even if, then it would be unmaintainable), and b) the
> implementation is hard to maintain/improve.
> This patch provides a programmatic implementation of CAS, similar
> like many other architectures are having one.
I noticed that when the address isn't already valid for lr/sc then we end
up with extra instructions to fix the address. For instance, using
gcc/testsuite/gcc.dg/atomic-compare-exchange-3.c, I get for the lr/sc loop
.L2:
addi a5,a3,%lo(v)
lr.w a1, 0(a5)
bne a1,a2,.L7
addi a1,a3,%lo(v)
sc.w a5, a0, 0(a1)
sext.w a5,a5
bne a5,zero,.L2
and note that there are two addi %lo instructions. The current code gives
addi a4,a4,%lo(v)
1: lr.w a2,0(a4); bne a2,a5,1f; sc.w a6,a0,0(a4); bnez a6,1b; 1:
which is better, as the address is fixed before the lr/sc loop.
The sext is fixed by the REE patch, or by directly generating the
sign-extending sc.w so that isn't an issue here.
Jim
next prev parent reply other threads:[~2021-04-27 15:17 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-26 12:45 [PATCH 00/10] [RISC-V] Atomics improvements [PR100265/PR100266] Christoph Muellner
2021-04-26 12:45 ` [PATCH 01/10] RISC-V: Simplify memory model code [PR 100265] Christoph Muellner
2021-04-26 12:45 ` [PATCH 02/10] RISC-V: Emit proper memory ordering suffixes for AMOs " Christoph Muellner
2021-04-26 12:45 ` [PATCH 03/10] RISC-V: Eliminate %F specifier from riscv_print_operand() " Christoph Muellner
2021-04-26 12:45 ` [PATCH 04/10] RISC-V: Don't use amoswap for atomic stores " Christoph Muellner
2021-04-26 12:45 ` [PATCH 05/10] RISC-V: Emit fences according to chosen memory model " Christoph Muellner
2021-04-26 12:45 ` [PATCH 06/10] RISC-V: Implement atomic_{load,store} " Christoph Muellner
2021-04-26 12:45 ` [PATCH 07/10] RISC-V: Model INSNs for LR and SC [PR 100266] Christoph Muellner
2021-04-26 12:45 ` [PATCH 08/10] RISC-V: Add s.ext-consuming " Christoph Muellner
2021-04-26 12:45 ` [PATCH 09/10] RISC-V: Generate helpers for cbranch4 " Christoph Muellner
2021-04-26 14:39 ` Kito Cheng
2021-05-05 19:26 ` Christoph Müllner
2021-04-26 12:45 ` [PATCH 10/10] RISC-V: Provide programmatic implementation of CAS " Christoph Muellner
2021-04-27 15:17 ` Jim Wilson [this message]
2021-04-28 22:40 ` [PATCH 00/10] [RISC-V] Atomics improvements [PR100265/PR100266] Jim Wilson
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