From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18819 invoked by alias); 24 Oct 2014 06:33:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 18808 invoked by uid 89); 24 Oct 2014 06:33:27 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-yh0-f47.google.com Received: from mail-yh0-f47.google.com (HELO mail-yh0-f47.google.com) (209.85.213.47) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Fri, 24 Oct 2014 06:33:25 +0000 Received: by mail-yh0-f47.google.com with SMTP id c41so3135422yho.6 for ; Thu, 23 Oct 2014 23:33:23 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.170.135.82 with SMTP id b79mr3320160ykc.77.1414132403309; Thu, 23 Oct 2014 23:33:23 -0700 (PDT) Received: by 10.31.179.66 with HTTP; Thu, 23 Oct 2014 23:33:23 -0700 (PDT) In-Reply-To: References: Date: Fri, 24 Oct 2014 06:40:00 -0000 Message-ID: Subject: Re: [PATCH] Add zero-overhead looping for xtensa backend From: "augustine.sterling@gmail.com" To: "Yangfei (Felix)" Cc: "gcc-patches@gcc.gnu.org" , Felix Yang Content-Type: text/plain; charset=UTF-8 X-SW-Source: 2014-10/txt/msg02473.txt.bz2 I mean without your patch at all. On Thu, Oct 23, 2014 at 11:30 PM, Yangfei (Felix) wrote: >> >> On Thu, Oct 23, 2014 at 9:12 PM, Yangfei (Felix) wrote: >> >> Here the key point is we need a general purpose register for the "loop" >> >> instruction. >> >> So the question to ask here is, "How does this work today, without loop >> instructions?" Somehow--even when it has been spilled--a branch instruction can >> test the trip count. There should be no difference. >> >> >> And we cannot use zero-cost looping in this situation. >> >> And that's why I spilt the zero_cost_loop_end into a normal test and branch. >> >> > Also note that the hwloop_pattern_reg interface also expects a general >> purpose register in the doloop_end pattern. >> >> If there were no loop instruction, how would this work? > > > Just take a look at my patch. I handle this in the new define_split: > > +(define_split > + [(set (pc) > + (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "") > + (const_int 1)) > + (label_ref (match_operand 1 "" "")) > + (pc))) > + (set (match_operand:SI 2 "nonimmediate_operand" "") > + (plus:SI (match_dup 0) > + (const_int -1))) > + (unspec [(const_int 0)] UNSPEC_LSETUP_END) > + (clobber (match_scratch 3))] > + "TARGET_LOOPS && optimize && reload_completed" > + [(const_int 0)] > +{ > + if (!REG_P (operands[0])) > + { > + rtx test; > + > + /* Fallback into a normal conditional branch insn. */ > + emit_move_insn (operands[3], operands[0]); > + emit_insn (gen_addsi3 (operands[3], operands[3], constm1_rtx)); > + emit_move_insn (operands[0], operands[3]); > + test = gen_rtx_NE (VOIDmode, operands[3], const0_rtx); > + emit_jump_insn (gen_cbranchsi4 (test, operands[3], > + const0_rtx, operands[1])); > + } > + else > + { > + emit_jump_insn (gen_loop_end (operands[0], operands[1], operands[2])); > + } > + > + DONE; > +})