From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 95468 invoked by alias); 12 Nov 2015 20:43:45 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 95458 invoked by uid 89); 12 Nov 2015 20:43:44 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lf0-f45.google.com Received: from mail-lf0-f45.google.com (HELO mail-lf0-f45.google.com) (209.85.215.45) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 12 Nov 2015 20:43:43 +0000 Received: by lffz63 with SMTP id z63so41410914lff.0 for ; Thu, 12 Nov 2015 12:43:40 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.25.18.209 with SMTP id 78mr8179297lfs.54.1447361020058; Thu, 12 Nov 2015 12:43:40 -0800 (PST) Received: by 10.114.71.114 with HTTP; Thu, 12 Nov 2015 12:43:40 -0800 (PST) In-Reply-To: <20151109004856.GG17170@ibm-tiger.the-meissners.org> References: <20151103202911.GA5304@ibm-tiger.the-meissners.org> <20151109004856.GG17170@ibm-tiger.the-meissners.org> Date: Thu, 12 Nov 2015 20:43:00 -0000 Message-ID: Subject: Re: [PATCH], Add power9 support to GCC, patch #7 (direct move enhancements) From: David Edelsohn To: Michael Meissner , GCC Patches Content-Type: text/plain; charset=UTF-8 X-SW-Source: 2015-11/txt/msg01593.txt.bz2 On Sun, Nov 8, 2015 at 7:48 PM, Michael Meissner wrote: > This patch adds support for the new direct move instructions (MFVSRLD and > MTVSRDD) that simplify moving 128-bit data between GPRs and vector registers. > > I have built previous versions of this patch with no regressions. At the > moment, I have built a non-bootstrap build and ran the PowerPC tests, with no > regressions. Assuming the bootstrap build that I've started has no > regressions, is it ok to install in the trunk? > > [gcc] > 2015-11-08 Michael Meissner > > * config/rs6000/constraints.md (we constraint): New constraint for > 64-bit power9 vector support. > (wL constraint): New constraint for the element in a vector that > can be addressed by the MFVSRLD instruction. > > * config/rs6000/rs6000.c (rs6000_debug_reg_global): Add ISA 3.0 > debugging. > (rs6000_init_hard_regno_mode_ok): If ISA 3.0 and 64-bit, enable we > constraint. Disable the VSX<->GPR direct move helpers if we have > the MFVSRLD and MTVSRDD instructions. > (rs6000_secondary_reload_simple_move): Add support for doing > vector direct moves directly without additional scratch registers > if we have ISA 3.0 instructions. > (rs6000_secondary_reload_direct_move): Update comments. > (rs6000_output_move_128bit): Add support for ISA 3.0 vector > instructions. > > * config/rs6000/vsx.md (vsx_mov): Add support for ISA 3.0 > direct move instructions. > (vsx_movti_64bit): Likewise. > (vsx_extract_): Likewise. > > * config/rs6000/rs6000.h (VECTOR_ELEMENT_MFVSRLD_64BIT): New > macros for ISA 3.0 direct move instructions. > (TARGET_DIRECT_MOVE_128): Likewise. > > * config/rs6000/rs6000.md (128-bit GPR splitters): Don't split a > 128-bit move that is a direct move between GPR and vector > registers using ISA 3.0 direct move instructions. > > * doc/md.texi (RS/6000 constraints): Document we, wF, wG, wL > constraints. Update wa documentation to say not to use %x on > instructions that only take Altivec registers. > > [gcc/testsuite] > 2015-11-08 Michael Meissner > > * gcc.target/powerpc/direct-move-vector.c: New test for 128-bit > vector direct move instructions. This is okay. Thanks, David