From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by sourceware.org (Postfix) with ESMTPS id A720D3858D38 for ; Mon, 9 Oct 2023 15:42:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A720D3858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-9ada2e6e75fso856499866b.2 for ; Mon, 09 Oct 2023 08:42:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696866139; x=1697470939; darn=gcc.gnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=apnIGezzOrpfuYKXNTB2P2djYzVxoiiJ47wUtDhSyGs=; b=I6pT/9xKP/2WE7RP/1SR0N9DfwTH1im9f0wPItA4jRH8WYyEs98G9/L8DPXRXzVoCp sunw4GS7zn2dEzReIXjbEAQjR3p4JDPAWs0r+9FEc6YdZe8vnL3etnIXthWvL5OMRYY4 IydAboS9CmLA4pZxulkoxScAzyv3nxBLZQAQMV0nklF/F0fhI/CFbf/xMe2cyi50B7Un IpU5OJAKbV/7QxIiuPju7GkjNaBHH1+f2upYW0PTiiq12paM3/rYECPzGQ3i3VOu7JbY hTGNLjQPrEdIQz7odgem16VaNMFW2pkt1gLh/sNJ2+zO9qkmhtAd+8tlsgbURxkHYFaj aeow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696866139; x=1697470939; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=apnIGezzOrpfuYKXNTB2P2djYzVxoiiJ47wUtDhSyGs=; b=P7460NGkFif79Mu5WBXk9STfAge374Lx7WLSQs08b2V2aoTeBbjhUEpKxfmgU5Y113 sEe9y65+sbemQrlUNWqNJCIVZoGjcStGfHTe/PYhCghqOrlVkZ5LQ60+i6shc3Fnga7F 2otXLg/X4yBOx2WkdVWvUmqV+zOMMHShv3JoROTIqe5jUq3mMsiisTFiJ7poB1/1iHQk zc0McVdN23Kv6O1b470nT+jgcvqOkwNjgOdAAoh6L89cFHtq7UEyM5kFb0rvxKxVaFwi 8JpVeeSIsXT0aDfUFTw4jLcVLfrMj4Azjkv033oFYe2QUXgasTHegr3HkP83ESoJpjvr i/kA== X-Gm-Message-State: AOJu0Yzue6rjZiihI06bdZCNvPyBXee5fvKCGxusMPu6ylA7fExPR2Xj dCy01e1ypVtCajYgBvlEeYo7rpij2RAjKiNUz1s= X-Google-Smtp-Source: AGHT+IE+9Km186ejs7F+lXOsI8eL4r5c2rkI8cI7eqtBrjPTyhEB/jsnvTu8nUVtZZdDiufEQfH4+NxgJH7ql2IKTk4= X-Received: by 2002:a17:907:2cd4:b0:9b9:facb:d956 with SMTP id hg20-20020a1709072cd400b009b9facbd956mr8342297ejc.5.1696866139030; Mon, 09 Oct 2023 08:42:19 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: David Edelsohn Date: Mon, 9 Oct 2023 11:42:07 -0400 Message-ID: Subject: Re: [PATCH-2, rs6000] Enable vector mode for memory equality compare [PR111449] To: HAO CHEN GUI Cc: gcc-patches , Segher Boessenkool , "Kewen.Lin" , Peter Bergner Content-Type: multipart/alternative; boundary="00000000000072ca6f06074a6f37" X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000072ca6f06074a6f37 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sun, Oct 8, 2023 at 10:30=E2=80=AFPM HAO CHEN GUI wrote: > Hi, > This patch enables vector mode for memory equality compare by adding > a new expand cbranchv16qi4 and implementing it. Also the corresponding > CC reg and compare code is set in rs6000_generate_compare. With the > patch, 16-byte equality compare can be implemented by one vector compare > instructions other than 2 8-byte compares with branches. > > The test case is in the second patch which is rs6000 specific. > > Bootstrapped and tested on powerpc64-linux BE and LE with no > regressions. > Thanks for working on this. > > Thanks > Gui Haochen > > ChangeLog > rs6000: Enable vector compare for memory equality compare > > gcc/ > PR target/111449 > * config/rs6000/altivec.md (cbranchv16qi4): New expand pattern. > * config/rs6000/rs6000.cc (rs6000_generate_compare): Generate insn > sequence for V16QImode equality compare. > * config/rs6000/rs6000.h (MOVE_MAX_PIECES): Define. > (COMPARE_MAX_PIECES): Define. > > gcc/testsuite/ > PR target/111449 > * gcc.target/powerpc/pr111449.c: New. > > patch.diff > diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md > index e8a596fb7e9..c69bf266402 100644 > --- a/gcc/config/rs6000/altivec.md > +++ b/gcc/config/rs6000/altivec.md > @@ -2605,6 +2605,39 @@ (define_insn "altivec_vupklpx" > } > [(set_attr "type" "vecperm")]) > > +(define_expand "cbranchv16qi4" > + [(use (match_operator 0 "equality_operator" > + [(match_operand:V16QI 1 "gpc_reg_operand") > + (match_operand:V16QI 2 "gpc_reg_operand")])) > + (use (match_operand 3))] > + "VECTOR_UNIT_ALTIVEC_P (V16QImode)" > +{ > + if (!TARGET_P9_VECTOR > + && MEM_P (operands[1]) > + && !altivec_indexed_or_indirect_operand (operands[1], V16QImode) > + && MEM_P (operands[2]) > + && !altivec_indexed_or_indirect_operand (operands[2], V16QImode)) > + { > + /* Use direct move as the byte order doesn't matter for equality > + compare. */ > + rtx reg_op1 =3D gen_reg_rtx (V16QImode); > + rtx reg_op2 =3D gen_reg_rtx (V16QImode); > + rs6000_emit_le_vsx_permute (reg_op1, operands[1], V16QImode); > + rs6000_emit_le_vsx_permute (reg_op2, operands[2], V16QImode); > + operands[1] =3D reg_op1; > + operands[2] =3D reg_op2; > + } > + else > + { > + operands[1] =3D force_reg (V16QImode, operands[1]); > + operands[2] =3D force_reg (V16QImode, operands[2]); > + } > + rtx_code code =3D GET_CODE (operands[0]); > + operands[0] =3D gen_rtx_fmt_ee (code, V16QImode, operands[1], > operands[2]); > + rs6000_emit_cbranch (V16QImode, operands); > + DONE; > +}) > + > ;; Compare vectors producing a vector result and a predicate, setting CR6 > to > ;; indicate a combined status > (define_insn "altivec_vcmpequ_p" > diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc > index efe9adce1f8..0087d786840 100644 > --- a/gcc/config/rs6000/rs6000.cc > +++ b/gcc/config/rs6000/rs6000.cc > @@ -15264,6 +15264,15 @@ rs6000_generate_compare (rtx cmp, machine_mode > mode) > else > emit_insn (gen_stack_protect_testsi (compare_result, op0, > op1b)); > } > + else if (mode =3D=3D V16QImode) > + { > + gcc_assert (code =3D=3D EQ || code =3D=3D NE); > + > + rtx result_vector =3D gen_reg_rtx (V16QImode); > + compare_result =3D gen_rtx_REG (CCmode, CR6_REGNO); > + emit_insn (gen_altivec_vcmpequb_p (result_vector, op0, op1)); > + code =3D (code =3D=3D NE) ? GE : LT; > + } > else > emit_insn (gen_rtx_SET (compare_result, > gen_rtx_COMPARE (comp_mode, op0, op1))); > diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h > index 3503614efbd..dc33bca0802 100644 > --- a/gcc/config/rs6000/rs6000.h > +++ b/gcc/config/rs6000/rs6000.h > @@ -1730,6 +1730,8 @@ typedef struct rs6000_args > in one reasonably fast instruction. */ > #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) > #define MAX_MOVE_MAX 8 > +#define MOVE_MAX_PIECES (!TARGET_POWERPC64 ? 4 : 16) > +#define COMPARE_MAX_PIECES (!TARGET_POWERPC64 ? 4 : 16) > How are the definitions of MOVE_MAX_PIECES and COMPARE_MAX_PIECES determined? The email does not provide any explanation for the implementation. The rest of the patch is related to vector support, but vector support is not dependent on TARGET_POWERPC64. Thanks, David > > /* Nonzero if access to memory by bytes is no faster than for words. > Also nonzero if doing byte operations (specifically shifts) in > registers > diff --git a/gcc/testsuite/gcc.target/powerpc/pr111449.c > b/gcc/testsuite/gcc.target/powerpc/pr111449.c > new file mode 100644 > index 00000000000..a8c30b92a41 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr111449.c > @@ -0,0 +1,19 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target powerpc_p8vector_ok } */ > +/* { dg-options "-maltivec -O2" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > + > +/* Ensure vector comparison is used for 16-byte memory equality compare. > */ > + > +int compare1 (const char* s1, const char* s2) > +{ > + return __builtin_memcmp (s1, s2, 16) =3D=3D 0; > +} > + > +int compare2 (const char* s1) > +{ > + return __builtin_memcmp (s1, "0123456789012345", 16) =3D=3D 0; > +} > + > +/* { dg-final { scan-assembler-times {\mvcmpequb\.} 2 } } */ > +/* { dg-final { scan-assembler-not {\mcmpd\M} } } */ > --00000000000072ca6f06074a6f37--