* [PATCH 4/9] rs6000: Make all insert instructions one type
2014-05-23 6:13 [PATCH 1/9] rs6000: Clean up the "type" attribute Segher Boessenkool
2014-05-23 6:13 ` [PATCH 2/9] rs6000: New type attribute value "halfmul" Segher Boessenkool
@ 2014-05-23 6:13 ` Segher Boessenkool
2014-05-23 13:42 ` David Edelsohn
2014-05-23 6:13 ` [PATCH 3/9] rs6000: Make all multiply " Segher Boessenkool
` (6 subsequent siblings)
8 siblings, 1 reply; 20+ messages in thread
From: Segher Boessenkool @ 2014-05-23 6:13 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
This uses the attribute "size" to specify the differences:
insert_word -> insert size=32
insert_dword -> insert size=64
It could use "dot" as well, but the current code doesn't handle that.
2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
gcc/
* config/rs6000/rs6000.md (type): Delete "insert_word",
"insert_dword". Add "insert".
(size): Update comment.
* config/rs6000/rs6000.c (rs6000_adjust_cost, is_cracked_insn,
insn_must_be_first_in_group): Adjust.
(insvsi_internal, *insvsi_internal1, *insvsi_internal2,
*insvsi_internal3, *insvsi_internal4, *insvsi_internal5,
*insvsi_internal6, insvdi_internal): Adjust.
* config/rs6000/40x.md (ppc403-integer): Adjust.
* config/rs6000/440.md (ppc440-integer): Adjust.
* config/rs6000/476.md (ppc476-simple-integer): Adjust.
* config/rs6000/601.md (ppc601-integer): Adjust.
* config/rs6000/603.md (ppc603-integer): Adjust.
* config/rs6000/6xx.md (ppc604-integer): Adjust.
* config/rs6000/7450.md (ppc7450-integer): Adjust.
* config/rs6000/7xx.md (ppc750-integer): Adjust.
* config/rs6000/8540.md (ppc8540_su): Adjust.
* config/rs6000/cell.md (cell-integer, cell-insert): Adjust.
* config/rs6000/e300c2c3.md (ppce300c3_iu): Adjust.
* config/rs6000/e500mc.md (e500mc_su): Adjust.
* config/rs6000/e500mc64.md (e500mc64_su): Adjust.
* config/rs6000/e5500.md (e5500_sfx): Adjust.
* config/rs6000/e6500.md (e6500_sfx): Adjust.
* config/rs6000/mpc.md (mpccore-integer): Adjust.
* config/rs6000/power4.md (power4-integer, power4-insert): Adjust.
* config/rs6000/power5.md (power5-integer, power5-insert): Adjust.
* config/rs6000/power6.md (power6-insert, power6-insert-dword):
Adjust.
* config/rs6000/power7.md (power7-integer): Adjust.
* config/rs6000/power8.md (power8-1cyc): Adjust.
* config/rs6000/rs64.md (rs64a-integer): Adjust.
* config/rs6000/titan.md (titan_fxu_shift_and_rotate): Adjust.
---
gcc/config/rs6000/40x.md | 2 +-
gcc/config/rs6000/440.md | 2 +-
gcc/config/rs6000/476.md | 2 +-
gcc/config/rs6000/601.md | 2 +-
gcc/config/rs6000/603.md | 2 +-
gcc/config/rs6000/6xx.md | 2 +-
gcc/config/rs6000/7450.md | 2 +-
gcc/config/rs6000/7xx.md | 2 +-
gcc/config/rs6000/8540.md | 2 +-
gcc/config/rs6000/cell.md | 9 ++++++---
gcc/config/rs6000/e300c2c3.md | 2 +-
gcc/config/rs6000/e500mc.md | 2 +-
gcc/config/rs6000/e500mc64.md | 2 +-
gcc/config/rs6000/e5500.md | 2 +-
gcc/config/rs6000/e6500.md | 2 +-
gcc/config/rs6000/mpc.md | 2 +-
gcc/config/rs6000/power4.md | 9 ++++++---
gcc/config/rs6000/power5.md | 9 ++++++---
gcc/config/rs6000/power6.md | 6 ++++--
gcc/config/rs6000/power7.md | 2 +-
gcc/config/rs6000/power8.md | 2 +-
gcc/config/rs6000/rs6000.c | 12 +++++-------
gcc/config/rs6000/rs6000.md | 21 +++++++++++----------
gcc/config/rs6000/rs64.md | 2 +-
gcc/config/rs6000/titan.md | 2 +-
25 files changed, 57 insertions(+), 47 deletions(-)
diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md
index 7ec2801..02971cb 100644
--- a/gcc/config/rs6000/40x.md
+++ b/gcc/config/rs6000/40x.md
@@ -36,7 +36,7 @@ (define_insn_reservation "ppc403-store" 2
"iu_40x")
(define_insn_reservation "ppc403-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ (and (eq_attr "type" "integer,insert,shift,trap,\
var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md
index 55d1155..292177d 100644
--- a/gcc/config/rs6000/440.md
+++ b/gcc/config/rs6000/440.md
@@ -53,7 +53,7 @@ (define_insn_reservation "ppc440-fpstore" 3
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
+ (and (eq_attr "type" "integer,insert,shift,\
trap,var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md
index 7b00632..403752a 100644
--- a/gcc/config/rs6000/476.md
+++ b/gcc/config/rs6000/476.md
@@ -63,7 +63,7 @@ (define_insn_reservation "ppc476-fpstore" 4
ppc476_lj_pipe")
(define_insn_reservation "ppc476-simple-integer" 1
- (and (eq_attr "type" "integer,insert_word,var_shift_rotate,exts,shift")
+ (and (eq_attr "type" "integer,insert,var_shift_rotate,exts,shift")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe|ppc476_lj_pipe")
diff --git a/gcc/config/rs6000/601.md b/gcc/config/rs6000/601.md
index c1a0043..d0afcf7 100644
--- a/gcc/config/rs6000/601.md
+++ b/gcc/config/rs6000/601.md
@@ -45,7 +45,7 @@ (define_insn_reservation "ppc601-fpstore" 3
"iu_ppc601+fpu_ppc601")
(define_insn_reservation "ppc601-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
+ (and (eq_attr "type" "integer,insert,shift,\
trap,var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc601"))
"iu_ppc601")
diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md
index 7e411264..e6cc444 100644
--- a/gcc/config/rs6000/603.md
+++ b/gcc/config/rs6000/603.md
@@ -58,7 +58,7 @@ (define_insn_reservation "ppc603-storec" 8
"lsu_603")
(define_insn_reservation "ppc603-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ (and (eq_attr "type" "integer,insert,shift,trap,\
var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc603"))
"iu_603")
diff --git a/gcc/config/rs6000/6xx.md b/gcc/config/rs6000/6xx.md
index 429e862..3a3271e 100644
--- a/gcc/config/rs6000/6xx.md
+++ b/gcc/config/rs6000/6xx.md
@@ -73,7 +73,7 @@ (define_insn_reservation "ppc630-llsc" 4
"lsu_6xx")
(define_insn_reservation "ppc604-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ (and (eq_attr "type" "integer,insert,shift,trap,\
var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md
index b7b5efd..a6a4a1b 100644
--- a/gcc/config/rs6000/7450.md
+++ b/gcc/config/rs6000/7450.md
@@ -73,7 +73,7 @@ (define_insn_reservation "ppc7450-sync" 35
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
+ (and (eq_attr "type" "integer,insert,shift,\
trap,var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md
index 059d006..332a663 100644
--- a/gcc/config/rs6000/7xx.md
+++ b/gcc/config/rs6000/7xx.md
@@ -61,7 +61,7 @@ (define_insn_reservation "ppc750-storec" 8
"ppc750_du,lsu_7xx")
(define_insn_reservation "ppc750-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
+ (and (eq_attr "type" "integer,insert,shift,\
trap,var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx")
diff --git a/gcc/config/rs6000/8540.md b/gcc/config/rs6000/8540.md
index da3f92b..53545ee 100644
--- a/gcc/config/rs6000/8540.md
+++ b/gcc/config/rs6000/8540.md
@@ -84,7 +84,7 @@ (define_reservation "ppc8540_su_stage0"
;; Simple SU insns
(define_insn_reservation "ppc8540_su" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\
+ (and (eq_attr "type" "integer,insert,cmp,compare,\
delayed_compare,var_delayed_compare,fast_compare,\
shift,trap,var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc8540,ppc8548"))
diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md
index 8c3c741..3a2668f 100644
--- a/gcc/config/rs6000/cell.md
+++ b/gcc/config/rs6000/cell.md
@@ -166,8 +166,10 @@ (define_insn_reservation "cell-vecstore" 1
;; Integer latency is 2 cycles
(define_insn_reservation "cell-integer" 2
- (and (eq_attr "type" "integer,insert_dword,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,shift,trap,\
+ var_shift_rotate,cntlz,exts,isel")
+ (and (eq_attr "type" "insert")
+ (eq_attr "size" "64")))
(eq_attr "cpu" "cell"))
"slot01,fxu_cell")
@@ -185,7 +187,8 @@ (define_insn_reservation "cell-three" 6
;; rlwimi, alter cr0
(define_insn_reservation "cell-insert" 2
- (and (eq_attr "type" "insert_word")
+ (and (eq_attr "type" "insert")
+ (eq_attr "size" "32")
(eq_attr "cpu" "cell"))
"slot01,fxu_cell")
diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md
index aba0d20..e9c8f18 100644
--- a/gcc/config/rs6000/e300c2c3.md
+++ b/gcc/config/rs6000/e300c2c3.md
@@ -90,7 +90,7 @@ (define_insn_reservation "ppce300c3_cmp" 1
;; Other one cycle IU insns
(define_insn_reservation "ppce300c3_iu" 1
- (and (eq_attr "type" "integer,insert_word,isel")
+ (and (eq_attr "type" "integer,insert,isel")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
diff --git a/gcc/config/rs6000/e500mc.md b/gcc/config/rs6000/e500mc.md
index 051394e..426903d 100644
--- a/gcc/config/rs6000/e500mc.md
+++ b/gcc/config/rs6000/e500mc.md
@@ -70,7 +70,7 @@ (define_reservation "e500mc_su_stage0"
;; Simple SU insns.
(define_insn_reservation "e500mc_su" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\
+ (and (eq_attr "type" "integer,insert,cmp,compare,\
delayed_compare,var_delayed_compare,fast_compare,\
shift,trap,var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppce500mc"))
diff --git a/gcc/config/rs6000/e500mc64.md b/gcc/config/rs6000/e500mc64.md
index 3fcd94e..584aef3 100644
--- a/gcc/config/rs6000/e500mc64.md
+++ b/gcc/config/rs6000/e500mc64.md
@@ -69,7 +69,7 @@ (define_reservation "e500mc64_su_stage0"
;; Simple SU insns.
(define_insn_reservation "e500mc64_su" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
+ (and (eq_attr "type" "integer,insert,delayed_compare,\
shift,cntlz,exts")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
diff --git a/gcc/config/rs6000/e5500.md b/gcc/config/rs6000/e5500.md
index b04d0a3..fd79ca5 100644
--- a/gcc/config/rs6000/e5500.md
+++ b/gcc/config/rs6000/e5500.md
@@ -56,7 +56,7 @@ (define_reservation "e5500_sfx"
;; SFX.
(define_insn_reservation "e5500_sfx" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
+ (and (eq_attr "type" "integer,insert,delayed_compare,\
shift,cntlz,exts")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md
index 18a372b..b84f703 100644
--- a/gcc/config/rs6000/e6500.md
+++ b/gcc/config/rs6000/e6500.md
@@ -59,7 +59,7 @@ (define_reservation "e6500_sfx"
;; SFX.
(define_insn_reservation "e6500_sfx" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
+ (and (eq_attr "type" "integer,insert,delayed_compare,\
shift,cntlz,exts")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md
index 317d064..c4dff56 100644
--- a/gcc/config/rs6000/mpc.md
+++ b/gcc/config/rs6000/mpc.md
@@ -41,7 +41,7 @@ (define_insn_reservation "mpccore-fpload" 2
"lsu_mpc")
(define_insn_reservation "mpccore-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ (and (eq_attr "type" "integer,insert,shift,trap,\
var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "mpccore"))
"iu_mpc")
diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md
index 2f50851..f905a0d 100644
--- a/gcc/config/rs6000/power4.md
+++ b/gcc/config/rs6000/power4.md
@@ -210,8 +210,10 @@ (define_insn_reservation "power4-llsc" 11
; Integer latency is 2 cycles
(define_insn_reservation "power4-integer" 2
- (and (eq_attr "type" "integer,insert_dword,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,shift,trap,\
+ var_shift_rotate,cntlz,exts,isel")
+ (and (eq_attr "type" "insert")
+ (eq_attr "size" "64")))
(eq_attr "cpu" "power4"))
"iq_power4")
@@ -238,7 +240,8 @@ (define_insn_reservation "power4-three" 2
|(iu1_power4,nothing,iu1_power4,nothing,iu2_power4))")
(define_insn_reservation "power4-insert" 4
- (and (eq_attr "type" "insert_word")
+ (and (eq_attr "type" "insert")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
((iu1_power4,nothing,iu2_power4)\
diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md
index 3b855d3..407ec71 100644
--- a/gcc/config/rs6000/power5.md
+++ b/gcc/config/rs6000/power5.md
@@ -166,8 +166,10 @@ (define_insn_reservation "power5-llsc" 11
; Integer latency is 2 cycles
(define_insn_reservation "power5-integer" 2
- (and (eq_attr "type" "integer,insert_dword,shift,trap,\
- var_shift_rotate,cntlz,exts,isel,popcnt")
+ (and (ior (eq_attr "type" "integer,shift,trap,\
+ var_shift_rotate,cntlz,exts,isel,popcnt")
+ (and (eq_attr "type" "insert")
+ (eq_attr "size" "64")))
(eq_attr "cpu" "power5"))
"iq_power5")
@@ -194,7 +196,8 @@ (define_insn_reservation "power5-three" 2
|(iu1_power5,nothing,iu2_power5,nothing,iu2_power5))")
(define_insn_reservation "power5-insert" 4
- (and (eq_attr "type" "insert_word")
+ (and (eq_attr "type" "insert")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
diff --git a/gcc/config/rs6000/power6.md b/gcc/config/rs6000/power6.md
index bed2f9f..3a77fc5 100644
--- a/gcc/config/rs6000/power6.md
+++ b/gcc/config/rs6000/power6.md
@@ -247,12 +247,14 @@ (define_insn_reservation "power6-popcnt" 1
"FXU_power6")
(define_insn_reservation "power6-insert" 1
- (and (eq_attr "type" "insert_word")
+ (and (eq_attr "type" "insert")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power6"))
"FX2_power6")
(define_insn_reservation "power6-insert-dword" 1
- (and (eq_attr "type" "insert_dword")
+ (and (eq_attr "type" "insert")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power6"))
"FX2_power6")
diff --git a/gcc/config/rs6000/power7.md b/gcc/config/rs6000/power7.md
index be92bd5..d6ddc24 100644
--- a/gcc/config/rs6000/power7.md
+++ b/gcc/config/rs6000/power7.md
@@ -174,7 +174,7 @@ (define_insn_reservation "power7-sync" 11
; FX Unit
(define_insn_reservation "power7-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ (and (eq_attr "type" "integer,insert,shift,trap,\
var_shift_rotate,exts,isel,popcnt")
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md
index 024b972..f7bd9f8 100644
--- a/gcc/config/rs6000/power8.md
+++ b/gcc/config/rs6000/power8.md
@@ -168,7 +168,7 @@ (define_insn_reservation "power8-sync" 1
; FX Unit
(define_insn_reservation "power8-1cyc" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ (and (eq_attr "type" "integer,insert,shift,trap,\
var_shift_rotate,exts,isel")
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d040825..8d9eb4d 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -26239,8 +26239,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case TYPE_FAST_COMPARE:
case TYPE_EXTS:
case TYPE_SHIFT:
- case TYPE_INSERT_WORD:
- case TYPE_INSERT_DWORD:
+ case TYPE_INSERT:
{
if (! store_data_bypass_p (dep_insn, insn))
return 3;
@@ -26310,8 +26309,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case TYPE_FAST_COMPARE:
case TYPE_EXTS:
case TYPE_SHIFT:
- case TYPE_INSERT_WORD:
- case TYPE_INSERT_DWORD:
+ case TYPE_INSERT:
{
if (set_to_load_agen (dep_insn, insn))
return 3;
@@ -26494,7 +26492,8 @@ is_cracked_insn (rtx insn)
|| (type == TYPE_MUL
&& get_attr_dot (insn) == DOT_YES)
|| type == TYPE_IDIV || type == TYPE_LDIV
- || type == TYPE_INSERT_WORD)
+ || (type == TYPE_INSERT
+ && get_attr_size (insn) == SIZE_32))
return true;
}
@@ -27319,7 +27318,6 @@ insn_must_be_first_in_group (rtx insn)
switch (type)
{
- case TYPE_INSERT_DWORD:
case TYPE_EXTS:
case TYPE_CNTLZ:
case TYPE_SHIFT:
@@ -27327,7 +27325,7 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_TRAP:
case TYPE_MUL:
case TYPE_IDIV:
- case TYPE_INSERT_WORD:
+ case TYPE_INSERT:
case TYPE_DELAYED_COMPARE:
case TYPE_FPCOMPARE:
case TYPE_MFCR:
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index fc46d11..28410e7 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -159,7 +159,7 @@ (define_c_enum "unspecv"
;; computations.
(define_attr "type"
"integer,two,three,
- shift,var_shift_rotate,insert_word,insert_dword,
+ shift,var_shift_rotate,insert,
mul,halfmul,idiv,ldiv,
exts,cntlz,popcnt,isel,
load,store,fpload,fpstore,vecload,vecstore,
@@ -175,7 +175,7 @@ (define_attr "type"
(const_string "integer"))
;; What data size does this instruction work on?
-;; This is used for mul.
+;; This is used for insert, mul.
(define_attr "size" "8,16,32,64" (const_string "32"))
;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
@@ -3417,7 +3417,7 @@ (define_insn "insvsi_internal"
operands[1] = GEN_INT (start + size - 1);
return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
- [(set_attr "type" "insert_word")])
+ [(set_attr "type" "insert")])
(define_insn "*insvsi_internal1"
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
@@ -3436,7 +3436,7 @@ (define_insn "*insvsi_internal1"
operands[1] = GEN_INT (start + size - 1);
return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
- [(set_attr "type" "insert_word")])
+ [(set_attr "type" "insert")])
(define_insn "*insvsi_internal2"
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
@@ -3455,7 +3455,7 @@ (define_insn "*insvsi_internal2"
operands[1] = GEN_INT (start + size - 1);
return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
- [(set_attr "type" "insert_word")])
+ [(set_attr "type" "insert")])
(define_insn "*insvsi_internal3"
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
@@ -3474,7 +3474,7 @@ (define_insn "*insvsi_internal3"
operands[1] = GEN_INT (start + size - 1);
return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
- [(set_attr "type" "insert_word")])
+ [(set_attr "type" "insert")])
(define_insn "*insvsi_internal4"
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
@@ -3496,7 +3496,7 @@ (define_insn "*insvsi_internal4"
operands[1] = GEN_INT (insert_start + insert_size - 1);
return \"rlwimi %0,%3,%h5,%h2,%h1\";
}"
- [(set_attr "type" "insert_word")])
+ [(set_attr "type" "insert")])
;; combine patterns for rlwimi
(define_insn "*insvsi_internal5"
@@ -3516,7 +3516,7 @@ (define_insn "*insvsi_internal5"
operands[1] = GEN_INT(me);
return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
- [(set_attr "type" "insert_word")])
+ [(set_attr "type" "insert")])
(define_insn "*insvsi_internal6"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -3535,7 +3535,7 @@ (define_insn "*insvsi_internal6"
operands[1] = GEN_INT(me);
return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
- [(set_attr "type" "insert_word")])
+ [(set_attr "type" "insert")])
(define_insn "insvdi_internal"
[(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
@@ -3551,7 +3551,8 @@ (define_insn "insvdi_internal"
operands[1] = GEN_INT (64 - start - size);
return \"rldimi %0,%3,%H1,%H2\";
}"
- [(set_attr "type" "insert_dword")])
+ [(set_attr "type" "insert")
+ (set_attr "size" "64")])
(define_insn "*insvdi_internal2"
[(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md
index 76113e8..aaddb59 100644
--- a/gcc/config/rs6000/rs64.md
+++ b/gcc/config/rs6000/rs64.md
@@ -46,7 +46,7 @@ (define_insn_reservation "rs64a-llsc" 2
"lsu_rs64")
(define_insn_reservation "rs64a-integer" 1
- (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ (and (eq_attr "type" "integer,insert,shift,trap,\
var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "rs64a"))
"iu_rs64")
diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md
index 21186a3..6c7516d 100644
--- a/gcc/config/rs6000/titan.md
+++ b/gcc/config/rs6000/titan.md
@@ -51,7 +51,7 @@ (define_insn_reservation "titan_mulhw" 4
(define_bypass 2 "titan_mulhw" "titan_mulhw")
(define_insn_reservation "titan_fxu_shift_and_rotate" 2
- (and (eq_attr "type" "insert_word,shift,var_shift_rotate,cntlz")
+ (and (eq_attr "type" "insert,shift,var_shift_rotate,cntlz")
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing*2,titan_fxu_wb")
--
1.8.1.4
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 2/9] rs6000: New type attribute value "halfmul"
2014-05-23 6:13 [PATCH 1/9] rs6000: Clean up the "type" attribute Segher Boessenkool
@ 2014-05-23 6:13 ` Segher Boessenkool
2014-05-23 13:37 ` David Edelsohn
2014-05-23 6:13 ` [PATCH 4/9] rs6000: Make all insert instructions one type Segher Boessenkool
` (7 subsequent siblings)
8 siblings, 1 reply; 20+ messages in thread
From: Segher Boessenkool @ 2014-05-23 6:13 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
This is for the legacy integer multiply-accumulate instructions.
Quite a mouthful, and "mulhw" is also a terrible name since we already
have a machine instruction called exactly that. Hence "halfmul".
Also fixes the titan automaton description for this.
2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
gcc/
* config/rs6000/rs6000.md (type): Add new value "halfmul".
(*macchwc, *macchw, *macchwuc, *macchwu, *machhwc, *machhw,
*machhwuc, *machhwu, *maclhwc, *maclhw, *maclhwuc, *maclhwu,
*nmacchwc, *nmacchw, *nmachhwc, *nmachhw, *nmaclhwc, *nmaclhw,
*mulchwc, *mulchw, *mulchwuc, *mulchwu, *mulhhwc, *mulhhw,
*mulhhwuc, *mulhhwu, *mullhwc, *mullhw, *mullhwuc, *mullhwu):
Use it.
* config/rs6000/40x.md (ppc405-imul3): Add type halfmul.
* config/rs6000/440.md (ppc440-imul2): Add type halfmul.
* config/rs6000/476.md (ppc476-imul): Add type halfmul.
* config/rs6000/titan.md: Delete nonsensical comment.
(titan_imul): Add type imul3.
(titan_mulhw): Remove type imul3; add type halfmul.
---
gcc/config/rs6000/40x.md | 2 +-
gcc/config/rs6000/440.md | 2 +-
gcc/config/rs6000/476.md | 2 +-
gcc/config/rs6000/rs6000.md | 62 ++++++++++++++++++++++-----------------------
gcc/config/rs6000/titan.md | 8 ++----
5 files changed, 36 insertions(+), 40 deletions(-)
diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md
index ed236a4..5510767 100644
--- a/gcc/config/rs6000/40x.md
+++ b/gcc/config/rs6000/40x.md
@@ -73,7 +73,7 @@ (define_insn_reservation "ppc405-imul2" 3
"iu_40x*2")
(define_insn_reservation "ppc405-imul3" 2
- (and (eq_attr "type" "imul3")
+ (and (eq_attr "type" "imul3,halfmul")
(eq_attr "cpu" "ppc405"))
"iu_40x")
diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md
index 2dcc58d..df3a3b5 100644
--- a/gcc/config/rs6000/440.md
+++ b/gcc/config/rs6000/440.md
@@ -76,7 +76,7 @@ (define_insn_reservation "ppc440-imul" 3
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-imul2" 2
- (and (eq_attr "type" "imul2,imul3")
+ (and (eq_attr "type" "imul2,imul3,halfmul")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md
index 8b4e65f..acfe063 100644
--- a/gcc/config/rs6000/476.md
+++ b/gcc/config/rs6000/476.md
@@ -82,7 +82,7 @@ (define_insn_reservation "ppc476-compare" 4
ppc476_i_pipe")
(define_insn_reservation "ppc476-imul" 4
- (and (eq_attr "type" "imul,imul_compare,imul2,imul3")
+ (and (eq_attr "type" "imul,imul_compare,imul2,imul3,halfmul")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe")
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 667aac1..3e9686e 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -160,7 +160,7 @@ (define_c_enum "unspecv"
(define_attr "type"
"integer,two,three,
shift,var_shift_rotate,insert_word,insert_dword,
- imul,imul2,imul3,lmul,idiv,ldiv,
+ imul,imul2,imul3,lmul,halfmul,idiv,ldiv,
exts,cntlz,popcnt,isel,
load,store,fpload,fpstore,vecload,vecstore,
cmp,
@@ -1248,7 +1248,7 @@ (define_insn "*macchwc"
(match_dup 4)))]
"TARGET_MULHW"
"macchw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*macchw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1260,7 +1260,7 @@ (define_insn "*macchw"
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
"macchw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*macchwuc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1280,7 +1280,7 @@ (define_insn "*macchwuc"
(match_dup 4)))]
"TARGET_MULHW"
"macchwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*macchwu"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1292,7 +1292,7 @@ (define_insn "*macchwu"
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
"macchwu %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*machhwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1314,7 +1314,7 @@ (define_insn "*machhwc"
(match_dup 4)))]
"TARGET_MULHW"
"machhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*machhw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1327,7 +1327,7 @@ (define_insn "*machhw"
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
"machhw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*machhwuc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1349,7 +1349,7 @@ (define_insn "*machhwuc"
(match_dup 4)))]
"TARGET_MULHW"
"machhwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*machhwu"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1362,7 +1362,7 @@ (define_insn "*machhwu"
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
"machhwu %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*maclhwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1380,7 +1380,7 @@ (define_insn "*maclhwc"
(match_dup 4)))]
"TARGET_MULHW"
"maclhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*maclhw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1391,7 +1391,7 @@ (define_insn "*maclhw"
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
"maclhw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*maclhwuc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1409,7 +1409,7 @@ (define_insn "*maclhwuc"
(match_dup 4)))]
"TARGET_MULHW"
"maclhwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*maclhwu"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1420,7 +1420,7 @@ (define_insn "*maclhwu"
(match_operand:SI 3 "gpc_reg_operand" "0")))]
"TARGET_MULHW"
"maclhwu %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*nmacchwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1440,7 +1440,7 @@ (define_insn "*nmacchwc"
(match_dup 1)))))]
"TARGET_MULHW"
"nmacchw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*nmacchw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1452,7 +1452,7 @@ (define_insn "*nmacchw"
(match_operand:HI 1 "gpc_reg_operand" "r")))))]
"TARGET_MULHW"
"nmacchw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*nmachhwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1474,7 +1474,7 @@ (define_insn "*nmachhwc"
(const_int 16)))))]
"TARGET_MULHW"
"nmachhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*nmachhw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1487,7 +1487,7 @@ (define_insn "*nmachhw"
(const_int 16)))))]
"TARGET_MULHW"
"nmachhw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*nmaclhwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1505,7 +1505,7 @@ (define_insn "*nmaclhwc"
(match_dup 2)))))]
"TARGET_MULHW"
"nmaclhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*nmaclhw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1516,7 +1516,7 @@ (define_insn "*nmaclhw"
(match_operand:HI 2 "gpc_reg_operand" "r")))))]
"TARGET_MULHW"
"nmaclhw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulchwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1534,7 +1534,7 @@ (define_insn "*mulchwc"
(match_dup 1))))]
"TARGET_MULHW"
"mulchw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulchw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1545,7 +1545,7 @@ (define_insn "*mulchw"
(match_operand:HI 1 "gpc_reg_operand" "r"))))]
"TARGET_MULHW"
"mulchw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulchwuc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1563,7 +1563,7 @@ (define_insn "*mulchwuc"
(match_dup 1))))]
"TARGET_MULHW"
"mulchwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulchwu"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1574,7 +1574,7 @@ (define_insn "*mulchwu"
(match_operand:HI 1 "gpc_reg_operand" "r"))))]
"TARGET_MULHW"
"mulchwu %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulhhwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1594,7 +1594,7 @@ (define_insn "*mulhhwc"
(const_int 16))))]
"TARGET_MULHW"
"mulhhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulhhw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1606,7 +1606,7 @@ (define_insn "*mulhhw"
(const_int 16))))]
"TARGET_MULHW"
"mulhhw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulhhwuc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1626,7 +1626,7 @@ (define_insn "*mulhhwuc"
(const_int 16))))]
"TARGET_MULHW"
"mulhhwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mulhhwu"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1638,7 +1638,7 @@ (define_insn "*mulhhwu"
(const_int 16))))]
"TARGET_MULHW"
"mulhhwu %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mullhwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1654,7 +1654,7 @@ (define_insn "*mullhwc"
(match_dup 2))))]
"TARGET_MULHW"
"mullhw. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mullhw"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1664,7 +1664,7 @@ (define_insn "*mullhw"
(match_operand:HI 2 "gpc_reg_operand" "r"))))]
"TARGET_MULHW"
"mullhw %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mullhwuc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@@ -1680,7 +1680,7 @@ (define_insn "*mullhwuc"
(match_dup 2))))]
"TARGET_MULHW"
"mullhwu. %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
(define_insn "*mullhwu"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1690,7 +1690,7 @@ (define_insn "*mullhwu"
(match_operand:HI 2 "gpc_reg_operand" "r"))))]
"TARGET_MULHW"
"mullhwu %0,%1,%2"
- [(set_attr "type" "imul3")])
+ [(set_attr "type" "halfmul")])
\f
;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
(define_insn "dlmzb"
diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md
index 1adbee5..6bb4792 100644
--- a/gcc/config/rs6000/titan.md
+++ b/gcc/config/rs6000/titan.md
@@ -38,17 +38,13 @@ (define_insn_reservation "titan_fxu_adder" 1
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh")
-;; Keep the titan_imul and titan_mulhw (half-word) rules in order, to
-;; ensure the proper match: the half-word instructions are tagged as
-;; imul3 only, whereas regular multiplys will always carry a imul tag.
-
(define_insn_reservation "titan_imul" 5
- (and (eq_attr "type" "imul,imul2,imul_compare")
+ (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing*5,titan_fxu_wb")
(define_insn_reservation "titan_mulhw" 4
- (and (eq_attr "type" "imul3")
+ (and (eq_attr "type" "halfmul")
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing*4,titan_fxu_wb")
--
1.8.1.4
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/9] rs6000: Clean up the "type" attribute
@ 2014-05-23 6:13 Segher Boessenkool
2014-05-23 6:13 ` [PATCH 2/9] rs6000: New type attribute value "halfmul" Segher Boessenkool
` (8 more replies)
0 siblings, 9 replies; 20+ messages in thread
From: Segher Boessenkool @ 2014-05-23 6:13 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
Get rid of the one huge line. Group and order things a bit. Further
changes will follow so this doesn't try to make it perfect.
The rest of this patch series reduces the number of different integer
instruction types by folding many together using attributes "size"
(the data size), "dot" (does this instruction set CR0), and "var_shift"
(for shift instructions: is the shift amount from a register).
Many scheduling descriptions are incomplete; many instruction patterns
use the wrong instruction type. Hopefully things will be better if
there aren't that many different types to handle.
Each patch bootstrapped on powerpc64-linux, tested with
-m64,-m64/-mtune=power8,-m32,-m32/-mpowerpc64; no regressions (and
nothing magically fixed either).
Okay to apply?
Segher
2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
gcc/
* config/rs6000/rs6000.md (type): Reorder, reformat.
---
gcc/config/rs6000/rs6000.md | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 300bd36..667aac1 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -157,7 +157,22 @@ (define_c_enum "unspecv"
\f
;; Define an insn type attribute. This is used in function unit delay
;; computations.
-(define_attr "type" "integer,two,three,load,store,fpload,fpstore,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto,htm"
+(define_attr "type"
+ "integer,two,three,
+ shift,var_shift_rotate,insert_word,insert_dword,
+ imul,imul2,imul3,lmul,idiv,ldiv,
+ exts,cntlz,popcnt,isel,
+ load,store,fpload,fpstore,vecload,vecstore,
+ cmp,
+ branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
+ compare,fast_compare,delayed_compare,var_delayed_compare,
+ imul_compare,lmul_compare,
+ cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
+ fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
+ brinc,
+ vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
+ vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
+ htm"
(const_string "integer"))
;; Does this instruction sign-extend its result?
--
1.8.1.4
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 3/9] rs6000: Make all multiply instructions one type
2014-05-23 6:13 [PATCH 1/9] rs6000: Clean up the "type" attribute Segher Boessenkool
2014-05-23 6:13 ` [PATCH 2/9] rs6000: New type attribute value "halfmul" Segher Boessenkool
2014-05-23 6:13 ` [PATCH 4/9] rs6000: Make all insert instructions one type Segher Boessenkool
@ 2014-05-23 6:13 ` Segher Boessenkool
2014-05-23 13:40 ` David Edelsohn
2014-05-23 16:23 ` Pat Haugen
2014-05-23 6:56 ` [PATCH 7/9] rs6000: Make all add " Segher Boessenkool
` (5 subsequent siblings)
8 siblings, 2 replies; 20+ messages in thread
From: Segher Boessenkool @ 2014-05-23 6:13 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
This uses the attributes "size" and "dot" to specify the differences:
imul3 -> mul size=8
imul2 -> mul size=16
imul -> mul size=32
lmul -> mul size=64
imul_compare -> mul size=32 dot=yes
lmul_compare -> mul size=64 dot=yes
2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
gcc/
* config/rs6000/rs6000.md (type): Add "mul". Delete "imul",
"imul2", "imul3", "lmul", "imul_compare", "lmul_compare".
(size): New attribute.
(dot): New attribute.
(cell_micro): Adjust.
(mulsi3, *mulsi3_internal1, *mulsi3_internal2, mulsidi3,
umulsidi3, smulsi3_highpart, umulsi3_highpart, muldi3,
*muldi3_internal1, *muldi3_internal2, smuldi3_highpart,
umuldi3_highpart): Adjust.
* config/rs6000/rs6000.c (rs6000_adjust_cost, is_cracked_insn,
rs6000_adjust_priority, is_nonpipeline_insn,
insn_must_be_first_in_group, insn_must_be_last_in_group): Adjust.
* config/rs6000/40x.md (ppc403-imul, ppc405-imul, ppc405-imul2,
ppc405-imul3): Adjust.
* config/rs6000/440.md (ppc440-imul, ppc440-imul2): Adjust.
* config/rs6000/476.md (ppc476-imul): Adjust.
* config/rs6000/601.md (ppc601-imul): Adjust.
* config/rs6000/603.md (ppc603-imul, ppc603-imul2): Adjust.
* config/rs6000/6xx.md (ppc604-imul, ppc604e-imul, ppc620-imul,
ppc620-imul2, ppc620-imul3, ppc620-lmul): Adjust.
* config/rs6000/7450.md (ppc7450-imul, ppc7450-imul2): Adjust.
* config/rs6000/7xx.md (ppc750-imul, ppc750-imul2, ppc750-imul3):
Adjust.
* config/rs6000/8540.md (ppc8540_multiply): Adjust.
* config/rs6000/a2.md (ppca2-imul, ppca2-lmul): Adjust.
* config/rs6000/cell.md (cell-lmul, cell-lmul-cmp, cell-imul23,
cell-imul): Adjust.
* config/rs6000/e300c2c3.md (ppce300c3_multiply): Adjust.
* config/rs6000/e500mc.md (e500mc_multiply): Adjust.
* config/rs6000/e500mc64.md (e500mc64_multiply): Adjust.
* config/rs6000/e5500.md (e5500_multiply, e5500_multiply_i): Adjust.
* config/rs6000/e6500.md (e6500_multiply, e6500_multiply_i): Adjust.
* config/rs6000/mpc.md (mpccore-imul): Adjust.
* config/rs6000/power4.md (power4-lmul-cmp, power4-imul-cmp,
power4-lmul, power4-imul, power4-imul3): Adjust.
* config/rs6000/power5.md (power5-lmul-cmp, power5-imul-cmp,
power5-lmul, power5-imul, power5-imul3): Adjust.
* config/rs6000/power6.md (power6-lmul-cmp, power6-imul-cmp,
power6-lmul, power6-imul, power6-imul3): Adjust.
* config/rs6000/power7.md (power7-mul, power7-mul-compare): Adjust.
* config/rs6000/power8.md (power8-mul, power8-mul-compare): Adjust.
* config/rs6000/rs64.md (rs64a-imul, rs64a-imul2, rs64a-imul3,
rs64a-lmul): Adjust.
* config/rs6000/titan.md (titan_imul): Adjust.
---
gcc/config/rs6000/40x.md | 12 ++++++---
gcc/config/rs6000/440.md | 7 +++--
gcc/config/rs6000/476.md | 2 +-
gcc/config/rs6000/601.md | 2 +-
gcc/config/rs6000/603.md | 6 +++--
gcc/config/rs6000/6xx.md | 16 +++++++-----
gcc/config/rs6000/7450.md | 6 +++--
gcc/config/rs6000/7xx.md | 9 ++++---
gcc/config/rs6000/8540.md | 2 +-
gcc/config/rs6000/a2.md | 6 +++--
gcc/config/rs6000/cell.md | 15 ++++++++---
gcc/config/rs6000/e300c2c3.md | 2 +-
gcc/config/rs6000/e500mc.md | 2 +-
gcc/config/rs6000/e500mc64.md | 2 +-
gcc/config/rs6000/e5500.md | 8 ++++--
gcc/config/rs6000/e6500.md | 8 ++++--
gcc/config/rs6000/mpc.md | 2 +-
gcc/config/rs6000/power4.md | 19 ++++++++++----
gcc/config/rs6000/power5.md | 19 ++++++++++----
gcc/config/rs6000/power6.md | 19 ++++++++++----
gcc/config/rs6000/power7.md | 6 +++--
gcc/config/rs6000/power8.md | 6 +++--
gcc/config/rs6000/rs6000.c | 52 +++++++++++++-----------------------
gcc/config/rs6000/rs6000.md | 61 ++++++++++++++++++++++++++++---------------
gcc/config/rs6000/rs64.md | 12 ++++++---
gcc/config/rs6000/titan.md | 2 +-
26 files changed, 188 insertions(+), 115 deletions(-)
diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md
index 5510767..7ec2801 100644
--- a/gcc/config/rs6000/40x.md
+++ b/gcc/config/rs6000/40x.md
@@ -58,22 +58,26 @@ (define_insn_reservation "ppc403-compare" 3
"iu_40x,nothing,bpu_40x")
(define_insn_reservation "ppc403-imul" 4
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc403"))
"iu_40x*4")
(define_insn_reservation "ppc405-imul" 5
- (and (eq_attr "type" "imul,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppc405"))
"iu_40x*4")
(define_insn_reservation "ppc405-imul2" 3
- (and (eq_attr "type" "imul2")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "16")
(eq_attr "cpu" "ppc405"))
"iu_40x*2")
(define_insn_reservation "ppc405-imul3" 2
- (and (eq_attr "type" "imul3,halfmul")
+ (and (ior (eq_attr "type" "halfmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8")))
(eq_attr "cpu" "ppc405"))
"iu_40x")
diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md
index df3a3b5..55d1155 100644
--- a/gcc/config/rs6000/440.md
+++ b/gcc/config/rs6000/440.md
@@ -71,12 +71,15 @@ (define_insn_reservation "ppc440-three" 1
ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-imul" 3
- (and (eq_attr "type" "imul,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-imul2" 2
- (and (eq_attr "type" "imul2,imul3,halfmul")
+ (and (ior (eq_attr "type" "halfmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md
index acfe063..7b00632 100644
--- a/gcc/config/rs6000/476.md
+++ b/gcc/config/rs6000/476.md
@@ -82,7 +82,7 @@ (define_insn_reservation "ppc476-compare" 4
ppc476_i_pipe")
(define_insn_reservation "ppc476-imul" 4
- (and (eq_attr "type" "imul,imul_compare,imul2,imul3,halfmul")
+ (and (eq_attr "type" "mul,halfmul")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe")
diff --git a/gcc/config/rs6000/601.md b/gcc/config/rs6000/601.md
index 94ba06c..c1a0043 100644
--- a/gcc/config/rs6000/601.md
+++ b/gcc/config/rs6000/601.md
@@ -61,7 +61,7 @@ (define_insn_reservation "ppc601-three" 1
"iu_ppc601,iu_ppc601,iu_ppc601")
(define_insn_reservation "ppc601-imul" 5
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc601"))
"iu_ppc601*5")
diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md
index 2c778cd..7e411264 100644
--- a/gcc/config/rs6000/603.md
+++ b/gcc/config/rs6000/603.md
@@ -75,12 +75,14 @@ (define_insn_reservation "ppc603-three" 1
; This takes 2 or 3 cycles
(define_insn_reservation "ppc603-imul" 3
- (and (eq_attr "type" "imul,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppc603"))
"iu_603*2")
(define_insn_reservation "ppc603-imul2" 2
- (and (eq_attr "type" "imul2,imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16")
(eq_attr "cpu" "ppc603"))
"iu_603*2")
diff --git a/gcc/config/rs6000/6xx.md b/gcc/config/rs6000/6xx.md
index 88895a1..429e862 100644
--- a/gcc/config/rs6000/6xx.md
+++ b/gcc/config/rs6000/6xx.md
@@ -89,32 +89,36 @@ (define_insn_reservation "ppc604-three" 1
"iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-imul" 4
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc604"))
"mciu_6xx*2")
(define_insn_reservation "ppc604e-imul" 2
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc604e"))
"mciu_6xx")
(define_insn_reservation "ppc620-imul" 5
- (and (eq_attr "type" "imul,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*3")
(define_insn_reservation "ppc620-imul2" 4
- (and (eq_attr "type" "imul2")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "16")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*3")
(define_insn_reservation "ppc620-imul3" 3
- (and (eq_attr "type" "imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*3")
(define_insn_reservation "ppc620-lmul" 7
- (and (eq_attr "type" "lmul,lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "64")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*5")
diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md
index cae8c49..b7b5efd 100644
--- a/gcc/config/rs6000/7450.md
+++ b/gcc/config/rs6000/7450.md
@@ -90,12 +90,14 @@ (define_insn_reservation "ppc7450-three" 1
iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
(define_insn_reservation "ppc7450-imul" 4
- (and (eq_attr "type" "imul,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450*2")
(define_insn_reservation "ppc7450-imul2" 3
- (and (eq_attr "type" "imul2,imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450")
diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md
index 65934dd..059d006 100644
--- a/gcc/config/rs6000/7xx.md
+++ b/gcc/config/rs6000/7xx.md
@@ -77,17 +77,20 @@ (define_insn_reservation "ppc750-three" 1
"ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx")
(define_insn_reservation "ppc750-imul" 4
- (and (eq_attr "type" "imul,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx*4")
(define_insn_reservation "ppc750-imul2" 3
- (and (eq_attr "type" "imul2")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "16")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx*2")
(define_insn_reservation "ppc750-imul3" 2
- (and (eq_attr "type" "imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx")
diff --git a/gcc/config/rs6000/8540.md b/gcc/config/rs6000/8540.md
index 76cca3f..da3f92b 100644
--- a/gcc/config/rs6000/8540.md
+++ b/gcc/config/rs6000/8540.md
@@ -111,7 +111,7 @@ (define_insn_reservation "ppc8540_branch" 1
;; Multiply
(define_insn_reservation "ppc8540_multiply" 4
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
diff --git a/gcc/config/rs6000/a2.md b/gcc/config/rs6000/a2.md
index 02a9854..7cab4d3 100644
--- a/gcc/config/rs6000/a2.md
+++ b/gcc/config/rs6000/a2.md
@@ -48,13 +48,15 @@ (define_insn_reservation "ppca2-mtjmpr" 5
;; D.4.8
(define_insn_reservation "ppca2-imul" 1
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16,32")
(eq_attr "cpu" "ppca2"))
"nothing")
;; FIXME: latency and multiplier reservation for 64-bit multiply?
(define_insn_reservation "ppca2-lmul" 6
- (and (eq_attr "type" "lmul,lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "64")
(eq_attr "cpu" "ppca2"))
"mult*3")
diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md
index d13dcb6b..8c3c741 100644
--- a/gcc/config/rs6000/cell.md
+++ b/gcc/config/rs6000/cell.md
@@ -212,25 +212,32 @@ (define_insn_reservation "cell-cmp-microcoded" 9
;; mulld
(define_insn_reservation "cell-lmul" 15
- (and (eq_attr "type" "lmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "64")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*13")
;; mulld. is microcoded
(define_insn_reservation "cell-lmul-cmp" 22
- (and (eq_attr "type" "lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "size" "64")
(eq_attr "cpu" "cell"))
"slot0+slot1,nonpipeline,nonpipeline*20")
;; mulli, 6 cycles
(define_insn_reservation "cell-imul23" 6
- (and (eq_attr "type" "imul2,imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*4")
;; mullw, 9
(define_insn_reservation "cell-imul" 9
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "32")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*7")
diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md
index 7a54dba..aba0d20 100644
--- a/gcc/config/rs6000/e300c2c3.md
+++ b/gcc/config/rs6000/e300c2c3.md
@@ -102,7 +102,7 @@ (define_insn_reservation "ppce300c3_branch" 1
;; Multiply is non-pipelined but can be executed in any IU
(define_insn_reservation "ppce300c3_multiply" 2
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
ppce300c3_iu_stage0+ppce300c3_retire")
diff --git a/gcc/config/rs6000/e500mc.md b/gcc/config/rs6000/e500mc.md
index 7c14c63..051394e 100644
--- a/gcc/config/rs6000/e500mc.md
+++ b/gcc/config/rs6000/e500mc.md
@@ -91,7 +91,7 @@ (define_insn_reservation "e500mc_three" 1
;; Multiply.
(define_insn_reservation "e500mc_multiply" 4
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_mu_stage0,e500mc_mu_stage1,\
e500mc_mu_stage2,e500mc_mu_stage3+e500mc_retire")
diff --git a/gcc/config/rs6000/e500mc64.md b/gcc/config/rs6000/e500mc64.md
index 6418339..3fcd94e 100644
--- a/gcc/config/rs6000/e500mc64.md
+++ b/gcc/config/rs6000/e500mc64.md
@@ -99,7 +99,7 @@ (define_insn_reservation "e500mc64_three" 3
;; Multiply.
(define_insn_reservation "e500mc64_multiply" 4
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0,e500mc64_mu_stage1,\
e500mc64_mu_stage2,e500mc64_mu_stage3+e500mc64_retire")
diff --git a/gcc/config/rs6000/e5500.md b/gcc/config/rs6000/e5500.md
index 5164526..b04d0a3 100644
--- a/gcc/config/rs6000/e5500.md
+++ b/gcc/config/rs6000/e5500.md
@@ -101,12 +101,16 @@ (define_insn_reservation "e5500_mtjmpr" 1
;; CFX - Multiply.
(define_insn_reservation "e5500_multiply" 4
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1")
(define_insn_reservation "e5500_multiply_i" 5
- (and (eq_attr "type" "imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
+ (ior (eq_attr "dot" "yes")
+ (eq_attr "size" "8,16"))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_cfx_stage0,\
e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1")
diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md
index b2d8426..18a372b 100644
--- a/gcc/config/rs6000/e6500.md
+++ b/gcc/config/rs6000/e6500.md
@@ -104,12 +104,16 @@ (define_insn_reservation "e6500_mtjmpr" 1
;; CFX - Multiply.
(define_insn_reservation "e6500_multiply" 4
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_cfx_stage0,e6500_cfx_stage1")
(define_insn_reservation "e6500_multiply_i" 5
- (and (eq_attr "type" "imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
+ (ior (eq_attr "dot" "yes")
+ (eq_attr "size" "8,16"))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_cfx_stage0,\
e6500_cfx_stage0+e6500_cfx_stage1,e6500_cfx_stage1")
diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md
index bce5f85..317d064 100644
--- a/gcc/config/rs6000/mpc.md
+++ b/gcc/config/rs6000/mpc.md
@@ -57,7 +57,7 @@ (define_insn_reservation "mpccore-three" 1
"iu_mpc,iu_mpc,iu_mpc")
(define_insn_reservation "mpccore-imul" 2
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "mpccore"))
"mciu_mpc")
diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md
index bafb429..2f50851 100644
--- a/gcc/config/rs6000/power4.md
+++ b/gcc/config/rs6000/power4.md
@@ -261,7 +261,9 @@ (define_insn_reservation "power4-compare" 2
(define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
(define_insn_reservation "power4-lmul-cmp" 7
- (and (eq_attr "type" "lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
((iu1_power4*6,iu2_power4)\
@@ -271,7 +273,9 @@ (define_insn_reservation "power4-lmul-cmp" 7
(define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
(define_insn_reservation "power4-imul-cmp" 5
- (and (eq_attr "type" "imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
((iu1_power4*4,iu2_power4)\
@@ -281,19 +285,24 @@ (define_insn_reservation "power4-imul-cmp" 5
(define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
(define_insn_reservation "power4-lmul" 7
- (and (eq_attr "type" "lmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power4"))
"(du1_power4|du2_power4|du3_power4|du4_power4),\
(iu1_power4*6|iu2_power4*6)")
(define_insn_reservation "power4-imul" 5
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power4"))
"(du1_power4|du2_power4|du3_power4|du4_power4),\
(iu1_power4*4|iu2_power4*4)")
(define_insn_reservation "power4-imul3" 4
- (and (eq_attr "type" "imul2,imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16")
(eq_attr "cpu" "power4"))
"(du1_power4|du2_power4|du3_power4|du4_power4),\
(iu1_power4*3|iu2_power4*3)")
diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md
index 747fda3..3b855d3 100644
--- a/gcc/config/rs6000/power5.md
+++ b/gcc/config/rs6000/power5.md
@@ -211,31 +211,40 @@ (define_insn_reservation "power5-compare" 2
(define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
(define_insn_reservation "power5-lmul-cmp" 7
- (and (eq_attr "type" "lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5*6,iu2_power5")
(define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
(define_insn_reservation "power5-imul-cmp" 5
- (and (eq_attr "type" "imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5*4,iu2_power5")
(define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
(define_insn_reservation "power5-lmul" 7
- (and (eq_attr "type" "lmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power5"))
"(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*6|iu2_power5*6)")
(define_insn_reservation "power5-imul" 5
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power5"))
"(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*4|iu2_power5*4)")
(define_insn_reservation "power5-imul3" 4
- (and (eq_attr "type" "imul2,imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16")
(eq_attr "cpu" "power5"))
"(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*3|iu2_power5*3)")
diff --git a/gcc/config/rs6000/power6.md b/gcc/config/rs6000/power6.md
index 2947668..bed2f9f 100644
--- a/gcc/config/rs6000/power6.md
+++ b/gcc/config/rs6000/power6.md
@@ -357,31 +357,40 @@ (define_insn_reservation "power6-var-delayed-compare" 4
"FXU_power6")
(define_insn_reservation "power6-lmul-cmp" 16
- (and (eq_attr "type" "lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-imul-cmp" 16
- (and (eq_attr "type" "imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-lmul" 16
- (and (eq_attr "type" "lmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-imul" 16
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-imul3" 16
- (and (eq_attr "type" "imul2,imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
diff --git a/gcc/config/rs6000/power7.md b/gcc/config/rs6000/power7.md
index 35ac88e..be92bd5 100644
--- a/gcc/config/rs6000/power7.md
+++ b/gcc/config/rs6000/power7.md
@@ -207,12 +207,14 @@ (define_insn_reservation "power7-compare" 2
(define_bypass 3 "power7-cmp,power7-compare" "power7-crlogical,power7-delayedcr")
(define_insn_reservation "power7-mul" 4
- (and (eq_attr "type" "imul,imul2,imul3,lmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
(define_insn_reservation "power7-mul-compare" 5
- (and (eq_attr "type" "imul_compare,lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "power7"))
"DU2F_power7,FXU_power7,nothing*3,FXU_power7")
diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md
index 7af5eab..024b972 100644
--- a/gcc/config/rs6000/power8.md
+++ b/gcc/config/rs6000/power8.md
@@ -228,12 +228,14 @@ (define_bypass 5 "power8-fast-compare,power8-compare"
"power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")
(define_insn_reservation "power8-mul" 4
- (and (eq_attr "type" "imul,imul2,imul3,lmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
(define_insn_reservation "power8-mul-compare" 4
- (and (eq_attr "type" "imul_compare,lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "power8"))
"DU_cracked_power8,FXU_power8")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index f58ccd0..d040825 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -26188,12 +26188,15 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case TYPE_CMP:
case TYPE_COMPARE:
case TYPE_DELAYED_COMPARE:
- case TYPE_IMUL_COMPARE:
- case TYPE_LMUL_COMPARE:
case TYPE_FPCOMPARE:
case TYPE_CR_LOGICAL:
case TYPE_DELAYED_CR:
return cost + 2;
+ case TYPE_MUL:
+ if (get_attr_dot (dep_insn) == DOT_YES)
+ return cost + 2;
+ else
+ break;
default:
break;
}
@@ -26252,12 +26255,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
return 3;
break;
}
- case TYPE_IMUL:
- case TYPE_IMUL2:
- case TYPE_IMUL3:
- case TYPE_LMUL:
- case TYPE_IMUL_COMPARE:
- case TYPE_LMUL_COMPARE:
+ case TYPE_MUL:
{
if (! store_data_bypass_p (dep_insn, insn))
return 17;
@@ -26328,12 +26326,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
return 3;
break;
}
- case TYPE_IMUL:
- case TYPE_IMUL2:
- case TYPE_IMUL3:
- case TYPE_LMUL:
- case TYPE_IMUL_COMPARE:
- case TYPE_LMUL_COMPARE:
+ case TYPE_MUL:
{
if (set_to_load_agen (dep_insn, insn))
return 17;
@@ -26498,7 +26491,8 @@ is_cracked_insn (rtx insn)
&& get_attr_update (insn) == UPDATE_YES)
|| type == TYPE_DELAYED_CR
|| type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
- || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
+ || (type == TYPE_MUL
+ && get_attr_dot (insn) == DOT_YES)
|| type == TYPE_IDIV || type == TYPE_LDIV
|| type == TYPE_INSERT_WORD)
return true;
@@ -26654,7 +26648,7 @@ rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
default:
break;
- case TYPE_IMUL:
+ case TYPE_MUL:
case TYPE_IDIV:
fprintf (stderr, "priority was %#x (%d) before adjustment\n",
priority, priority);
@@ -26708,10 +26702,7 @@ is_nonpipeline_insn (rtx insn)
return false;
type = get_attr_type (insn);
- if (type == TYPE_IMUL
- || type == TYPE_IMUL2
- || type == TYPE_IMUL3
- || type == TYPE_LMUL
+ if (type == TYPE_MUL
|| type == TYPE_IDIV
|| type == TYPE_LDIV
|| type == TYPE_SDIV
@@ -27334,15 +27325,10 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_SHIFT:
case TYPE_VAR_SHIFT_ROTATE:
case TYPE_TRAP:
- case TYPE_IMUL:
- case TYPE_IMUL2:
- case TYPE_IMUL3:
- case TYPE_LMUL:
+ case TYPE_MUL:
case TYPE_IDIV:
case TYPE_INSERT_WORD:
case TYPE_DELAYED_COMPARE:
- case TYPE_IMUL_COMPARE:
- case TYPE_LMUL_COMPARE:
case TYPE_FPCOMPARE:
case TYPE_MFCR:
case TYPE_MTCR:
@@ -27385,6 +27371,11 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_MFJMPR:
case TYPE_MTJMPR:
return true;
+ case TYPE_MUL:
+ if (get_attr_dot (insn) == DOT_YES)
+ return true;
+ else
+ break;
case TYPE_LOAD:
if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
|| get_attr_update (insn) == UPDATE_YES)
@@ -27415,8 +27406,6 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_COMPARE:
case TYPE_DELAYED_COMPARE:
case TYPE_VAR_DELAYED_COMPARE:
- case TYPE_IMUL_COMPARE:
- case TYPE_LMUL_COMPARE:
case TYPE_SYNC:
case TYPE_ISYNC:
case TYPE_LOAD_L:
@@ -27480,14 +27469,9 @@ insn_must_be_last_in_group (rtx insn)
case TYPE_SHIFT:
case TYPE_VAR_SHIFT_ROTATE:
case TYPE_TRAP:
- case TYPE_IMUL:
- case TYPE_IMUL2:
- case TYPE_IMUL3:
- case TYPE_LMUL:
+ case TYPE_MUL:
case TYPE_IDIV:
case TYPE_DELAYED_COMPARE:
- case TYPE_IMUL_COMPARE:
- case TYPE_LMUL_COMPARE:
case TYPE_FPCOMPARE:
case TYPE_MFCR:
case TYPE_MTCR:
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3e9686e..fc46d11 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -160,13 +160,12 @@ (define_c_enum "unspecv"
(define_attr "type"
"integer,two,three,
shift,var_shift_rotate,insert_word,insert_dword,
- imul,imul2,imul3,lmul,halfmul,idiv,ldiv,
+ mul,halfmul,idiv,ldiv,
exts,cntlz,popcnt,isel,
load,store,fpload,fpstore,vecload,vecstore,
cmp,
branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
compare,fast_compare,delayed_compare,var_delayed_compare,
- imul_compare,lmul_compare,
cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
brinc,
@@ -175,6 +174,14 @@ (define_attr "type"
htm"
(const_string "integer"))
+;; What data size does this instruction work on?
+;; This is used for mul.
+(define_attr "size" "8,16,32,64" (const_string "32"))
+
+;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
+;; This is used for mul.
+(define_attr "dot" "no,yes" (const_string "no"))
+
;; Does this instruction sign-extend its result?
;; This is used for load insns.
(define_attr "sign_extend" "no,yes" (const_string "no"))
@@ -229,7 +236,9 @@ (define_attr "cpu"
;; If this instruction is microcoded on the CELL processor
; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
(define_attr "cell_micro" "not,conditional,always"
- (if_then_else (ior (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,var_shift_rotate,var_delayed_compare")
+ (if_then_else (ior (eq_attr "type" "compare,delayed_compare,var_shift_rotate,var_delayed_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes"))
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")))
(const_string "always")
@@ -2665,12 +2674,13 @@ (define_insn "mulsi3"
"@
mullw %0,%1,%2
mulli %0,%1,%2"
- [(set (attr "type")
+ [(set_attr "type" "mul")
+ (set (attr "size")
(cond [(match_operand:SI 2 "s8bit_cint_operand" "")
- (const_string "imul3")
+ (const_string "8")
(match_operand:SI 2 "short_cint_operand" "")
- (const_string "imul2")]
- (const_string "imul")))])
+ (const_string "16")]
+ (const_string "32")))])
(define_insn "*mulsi3_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -2682,7 +2692,8 @@ (define_insn "*mulsi3_internal1"
"@
mullw. %3,%1,%2
#"
- [(set_attr "type" "imul_compare")
+ [(set_attr "type" "mul")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -2710,7 +2721,8 @@ (define_insn "*mulsi3_internal2"
"@
mullw. %0,%1,%2
#"
- [(set_attr "type" "imul_compare")
+ [(set_attr "type" "mul")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -6600,7 +6612,7 @@ (define_insn "mulsidi3"
? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
: \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
}
- [(set_attr "type" "imul")
+ [(set_attr "type" "mul")
(set_attr "length" "8")])
(define_split
@@ -6634,7 +6646,7 @@ (define_insn "umulsidi3"
? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
: \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
}"
- [(set_attr "type" "imul")
+ [(set_attr "type" "mul")
(set_attr "length" "8")])
(define_split
@@ -6667,7 +6679,7 @@ (define_insn "smulsi3_highpart"
(const_int 32))))]
""
"mulhw %0,%1,%2"
- [(set_attr "type" "imul")])
+ [(set_attr "type" "mul")])
(define_insn "umulsi3_highpart"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -6679,7 +6691,7 @@ (define_insn "umulsi3_highpart"
(const_int 32))))]
""
"mulhwu %0,%1,%2"
- [(set_attr "type" "imul")])
+ [(set_attr "type" "mul")])
;; Shift by a variable amount is too complex to be worth open-coding. We
;; just handle shifts by constants.
@@ -6734,12 +6746,13 @@ (define_insn "muldi3"
"@
mulld %0,%1,%2
mulli %0,%1,%2"
- [(set (attr "type")
+ [(set_attr "type" "mul")
+ (set (attr "size")
(cond [(match_operand:SI 2 "s8bit_cint_operand" "")
- (const_string "imul3")
+ (const_string "8")
(match_operand:SI 2 "short_cint_operand" "")
- (const_string "imul2")]
- (const_string "lmul")))])
+ (const_string "16")]
+ (const_string "64")))])
(define_insn "*muldi3_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -6751,7 +6764,9 @@ (define_insn "*muldi3_internal1"
"@
mulld. %3,%1,%2
#"
- [(set_attr "type" "lmul_compare")
+ [(set_attr "type" "mul")
+ (set_attr "size" "64")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -6779,7 +6794,9 @@ (define_insn "*muldi3_internal2"
"@
mulld. %0,%1,%2
#"
- [(set_attr "type" "lmul_compare")
+ [(set_attr "type" "mul")
+ (set_attr "size" "64")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -6807,7 +6824,8 @@ (define_insn "smuldi3_highpart"
(const_int 64))))]
"TARGET_POWERPC64"
"mulhd %0,%1,%2"
- [(set_attr "type" "lmul")])
+ [(set_attr "type" "mul")
+ (set_attr "size" "64")])
(define_insn "umuldi3_highpart"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
@@ -6819,7 +6837,8 @@ (define_insn "umuldi3_highpart"
(const_int 64))))]
"TARGET_POWERPC64"
"mulhdu %0,%1,%2"
- [(set_attr "type" "lmul")])
+ [(set_attr "type" "mul")
+ (set_attr "size" "64")])
(define_expand "mulditi3"
[(set (match_operand:TI 0 "gpc_reg_operand")
diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md
index 977ed65..76113e8 100644
--- a/gcc/config/rs6000/rs64.md
+++ b/gcc/config/rs6000/rs64.md
@@ -62,22 +62,26 @@ (define_insn_reservation "rs64a-three" 1
"iu_rs64,iu_rs64,iu_rs64")
(define_insn_reservation "rs64a-imul" 20
- (and (eq_attr "type" "imul,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "32")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*13")
(define_insn_reservation "rs64a-imul2" 12
- (and (eq_attr "type" "imul2")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "16")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*5")
(define_insn_reservation "rs64a-imul3" 8
- (and (eq_attr "type" "imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*2")
(define_insn_reservation "rs64a-lmul" 34
- (and (eq_attr "type" "lmul,lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "64")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*34")
diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md
index 6bb4792..21186a3 100644
--- a/gcc/config/rs6000/titan.md
+++ b/gcc/config/rs6000/titan.md
@@ -39,7 +39,7 @@ (define_insn_reservation "titan_fxu_adder" 1
"titan_issue,titan_fxu_sh")
(define_insn_reservation "titan_imul" 5
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing*5,titan_fxu_wb")
--
1.8.1.4
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 5/9] rs6000: Make all divide instructions one type
2014-05-23 6:13 [PATCH 1/9] rs6000: Clean up the "type" attribute Segher Boessenkool
` (4 preceding siblings ...)
2014-05-23 6:56 ` [PATCH 8/9] rs6000: Make all logical " Segher Boessenkool
@ 2014-05-23 6:56 ` Segher Boessenkool
2014-05-23 13:46 ` David Edelsohn
2014-05-23 6:56 ` [PATCH 9/9] rs6000: Make all rlw*nm and rld*c* type shift Segher Boessenkool
` (2 subsequent siblings)
8 siblings, 1 reply; 20+ messages in thread
From: Segher Boessenkool @ 2014-05-23 6:56 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
This uses the attribute "size" to specify the differences:
idiv -> div size=32
ldiv -> div size=64
It could use "dot" as well, but the current code doesn't handle that.
2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
gcc/
* config/rs6000/rs6000.md (type): Delete "idiv", "ldiv". Add
"div".
(bits): New mode_attr.
(idiv_ldiv): Delete mode_attr.
(udiv<mode>3, *div<mode>3, div<div_extend>_<mode>): Adjust.
* config/rs6000/rs6000.c (rs6000_adjust_cost, is_cracked_insn,
rs6000_adjust_priority, is_nonpipeline_insn,
insn_must_be_first_in_group, insn_must_be_last_in_group): Adjust.
* config/rs6000/40x.md (ppc403-idiv): Adjust.
* config/rs6000/440.md (ppc440-idiv): Adjust.
* config/rs6000/476.md (ppc476-idiv): Adjust.
* config/rs6000/601.md (ppc601-idiv): Adjust.
* config/rs6000/603.md (ppc603-idiv): Adjust.
* config/rs6000/6xx.md (ppc604-idiv, ppc620-idiv, ppc630-idiv,
ppc620-ldiv): Adjust.
* config/rs6000/7450.md (ppc7450-idiv): Adjust.
* config/rs6000/7xx.md (ppc750-idiv): Adjust.
* config/rs6000/8540.md (ppc8540_divide): Adjust.
* config/rs6000/a2.md (ppca2-idiv, ppca2-ldiv): Adjust.
* config/rs6000/cell.md (cell-idiv, cell-ldiv): Adjust.
* config/rs6000/e300c2c3.md (ppce300c3_divide): Adjust.
* config/rs6000/e500mc.md (e500mc_divide): Adjust.
* config/rs6000/e500mc64.md (e500mc64_divide): Adjust.
* config/rs6000/e5500.md (e5500_divide, e5500_divide_d): Adjust.
* config/rs6000/e6500.md (e6500_divide, e6500_divide_d): Adjust.
* config/rs6000/mpc.md (mpccore-idiv): Adjust.
* config/rs6000/power4.md (power4-idiv, power4-ldiv): Adjust.
* config/rs6000/power5.md (power5-idiv, power5-ldiv): Adjust.
* config/rs6000/power6.md (power6-idiv, power6-ldiv): Adjust.
* config/rs6000/power7.md (power7-idiv, power7-ldiv): Adjust.
* config/rs6000/power8.md (power8-idiv, power8-ldiv): Adjust.
* config/rs6000/rs64.md (rs64a-idiv, rs64a-ldiv): Adjust.
* config/rs6000/titan.md (titan_fxu_div): Adjust.
---
gcc/config/rs6000/40x.md | 2 +-
gcc/config/rs6000/440.md | 2 +-
gcc/config/rs6000/476.md | 2 +-
gcc/config/rs6000/601.md | 2 +-
gcc/config/rs6000/603.md | 2 +-
gcc/config/rs6000/6xx.md | 11 +++++++----
gcc/config/rs6000/7450.md | 2 +-
gcc/config/rs6000/7xx.md | 2 +-
gcc/config/rs6000/8540.md | 2 +-
gcc/config/rs6000/a2.md | 6 ++++--
gcc/config/rs6000/cell.md | 6 ++++--
gcc/config/rs6000/e300c2c3.md | 2 +-
gcc/config/rs6000/e500mc.md | 2 +-
gcc/config/rs6000/e500mc64.md | 2 +-
gcc/config/rs6000/e5500.md | 6 ++++--
gcc/config/rs6000/e6500.md | 6 ++++--
gcc/config/rs6000/mpc.md | 2 +-
gcc/config/rs6000/power4.md | 6 ++++--
gcc/config/rs6000/power5.md | 6 ++++--
gcc/config/rs6000/power6.md | 6 ++++--
gcc/config/rs6000/power7.md | 6 ++++--
gcc/config/rs6000/power8.md | 6 ++++--
gcc/config/rs6000/rs6000.c | 45 ++++++++++++++++++-------------------------
gcc/config/rs6000/rs6000.md | 19 +++++++++---------
gcc/config/rs6000/rs64.md | 6 ++++--
gcc/config/rs6000/titan.md | 2 +-
26 files changed, 89 insertions(+), 72 deletions(-)
diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md
index 02971cb..8ddccba 100644
--- a/gcc/config/rs6000/40x.md
+++ b/gcc/config/rs6000/40x.md
@@ -82,7 +82,7 @@ (define_insn_reservation "ppc405-imul3" 2
"iu_40x")
(define_insn_reservation "ppc403-idiv" 33
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x*33")
diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md
index 292177d..e6c28a7 100644
--- a/gcc/config/rs6000/440.md
+++ b/gcc/config/rs6000/440.md
@@ -84,7 +84,7 @@ (define_insn_reservation "ppc440-imul2" 2
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-idiv" 34
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe*33")
diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md
index 403752a..5acd668 100644
--- a/gcc/config/rs6000/476.md
+++ b/gcc/config/rs6000/476.md
@@ -88,7 +88,7 @@ (define_insn_reservation "ppc476-imul" 4
ppc476_i_pipe")
(define_insn_reservation "ppc476-idiv" 11
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe*11")
diff --git a/gcc/config/rs6000/601.md b/gcc/config/rs6000/601.md
index d0afcf7..85892c8 100644
--- a/gcc/config/rs6000/601.md
+++ b/gcc/config/rs6000/601.md
@@ -66,7 +66,7 @@ (define_insn_reservation "ppc601-imul" 5
"iu_ppc601*5")
(define_insn_reservation "ppc601-idiv" 36
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
(eq_attr "cpu" "ppc601"))
"iu_ppc601*36")
diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md
index e6cc444..5f38741 100644
--- a/gcc/config/rs6000/603.md
+++ b/gcc/config/rs6000/603.md
@@ -87,7 +87,7 @@ (define_insn_reservation "ppc603-imul2" 2
"iu_603*2")
(define_insn_reservation "ppc603-idiv" 37
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
(eq_attr "cpu" "ppc603"))
"iu_603*37")
diff --git a/gcc/config/rs6000/6xx.md b/gcc/config/rs6000/6xx.md
index 3a3271e..3ff4caf 100644
--- a/gcc/config/rs6000/6xx.md
+++ b/gcc/config/rs6000/6xx.md
@@ -123,22 +123,25 @@ (define_insn_reservation "ppc620-lmul" 7
"mciu_6xx*5")
(define_insn_reservation "ppc604-idiv" 20
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
(eq_attr "cpu" "ppc604,ppc604e"))
"mciu_6xx*19")
(define_insn_reservation "ppc620-idiv" 37
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppc620"))
"mciu_6xx*36")
(define_insn_reservation "ppc630-idiv" 21
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppc630"))
"mciu_6xx*20")
(define_insn_reservation "ppc620-ldiv" 37
- (and (eq_attr "type" "ldiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "64")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*36")
diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md
index a6a4a1b..3333fd9 100644
--- a/gcc/config/rs6000/7450.md
+++ b/gcc/config/rs6000/7450.md
@@ -102,7 +102,7 @@ (define_insn_reservation "ppc7450-imul2" 3
"ppc7450_du,mciu_7450")
(define_insn_reservation "ppc7450-idiv" 23
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450*23")
diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md
index 332a663..67f3d11 100644
--- a/gcc/config/rs6000/7xx.md
+++ b/gcc/config/rs6000/7xx.md
@@ -95,7 +95,7 @@ (define_insn_reservation "ppc750-imul3" 2
"ppc750_du,iu1_7xx")
(define_insn_reservation "ppc750-idiv" 19
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx*19")
diff --git a/gcc/config/rs6000/8540.md b/gcc/config/rs6000/8540.md
index 53545ee..578cf8e 100644
--- a/gcc/config/rs6000/8540.md
+++ b/gcc/config/rs6000/8540.md
@@ -121,7 +121,7 @@ (define_insn_reservation "ppc8540_multiply" 4
;; reservation of miu_stage3 here because we use the average latency
;; time.
(define_insn_reservation "ppc8540_divide" 14
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
ppc8540_mu_div*13")
diff --git a/gcc/config/rs6000/a2.md b/gcc/config/rs6000/a2.md
index 7cab4d3..52dbbd4 100644
--- a/gcc/config/rs6000/a2.md
+++ b/gcc/config/rs6000/a2.md
@@ -62,12 +62,14 @@ (define_insn_reservation "ppca2-lmul" 6
;; D.4.9
(define_insn_reservation "ppca2-idiv" 32
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppca2"))
"mult*32")
(define_insn_reservation "ppca2-ldiv" 65
- (and (eq_attr "type" "ldiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "64")
(eq_attr "cpu" "ppca2"))
"mult*65")
diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md
index 3a2668f..1bf308e 100644
--- a/gcc/config/rs6000/cell.md
+++ b/gcc/config/rs6000/cell.md
@@ -246,12 +246,14 @@ (define_insn_reservation "cell-imul" 9
;; divide
(define_insn_reservation "cell-idiv" 32
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "32")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*30")
(define_insn_reservation "cell-ldiv" 64
- (and (eq_attr "type" "ldiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "64")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*62")
diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md
index e9c8f18..2abdfdb 100644
--- a/gcc/config/rs6000/e300c2c3.md
+++ b/gcc/config/rs6000/e300c2c3.md
@@ -110,7 +110,7 @@ (define_insn_reservation "ppce300c3_multiply" 2
;; Divide. We use the average latency time here. We omit reserving a
;; retire unit because of the result automata will be huge.
(define_insn_reservation "ppce300c3_divide" 20
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\
ppce300c3_mu_div*19")
diff --git a/gcc/config/rs6000/e500mc.md b/gcc/config/rs6000/e500mc.md
index 426903d..580c30d 100644
--- a/gcc/config/rs6000/e500mc.md
+++ b/gcc/config/rs6000/e500mc.md
@@ -98,7 +98,7 @@ (define_insn_reservation "e500mc_multiply" 4
;; Divide. We use the average latency time here.
(define_insn_reservation "e500mc_divide" 14
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_mu_stage0+e500mc_mu_div,\
e500mc_mu_div*13")
diff --git a/gcc/config/rs6000/e500mc64.md b/gcc/config/rs6000/e500mc64.md
index 584aef3..8844113 100644
--- a/gcc/config/rs6000/e500mc64.md
+++ b/gcc/config/rs6000/e500mc64.md
@@ -106,7 +106,7 @@ (define_insn_reservation "e500mc64_multiply" 4
;; Divide. We use the average latency time here.
(define_insn_reservation "e500mc64_divide" 14
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0+e500mc64_mu_div,\
e500mc64_mu_div*13")
diff --git a/gcc/config/rs6000/e5500.md b/gcc/config/rs6000/e5500.md
index fd79ca5..6b257d6 100644
--- a/gcc/config/rs6000/e5500.md
+++ b/gcc/config/rs6000/e5500.md
@@ -117,13 +117,15 @@ (define_insn_reservation "e5500_multiply_i" 5
;; CFX - Divide.
(define_insn_reservation "e5500_divide" 16
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
e5500_cfx_div*15")
(define_insn_reservation "e5500_divide_d" 26
- (and (eq_attr "type" "ldiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "64")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
e5500_cfx_div*25")
diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md
index b84f703..52565d9 100644
--- a/gcc/config/rs6000/e6500.md
+++ b/gcc/config/rs6000/e6500.md
@@ -120,13 +120,15 @@ (define_insn_reservation "e6500_multiply_i" 5
;; CFX - Divide.
(define_insn_reservation "e6500_divide" 16
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
e6500_cfx_div*15")
(define_insn_reservation "e6500_divide_d" 26
- (and (eq_attr "type" "ldiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "64")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
e6500_cfx_div*25")
diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md
index c4dff56..7fe889c 100644
--- a/gcc/config/rs6000/mpc.md
+++ b/gcc/config/rs6000/mpc.md
@@ -63,7 +63,7 @@ (define_insn_reservation "mpccore-imul" 2
; Divide latency varies greatly from 2-11, use 6 as average
(define_insn_reservation "mpccore-idiv" 6
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
(eq_attr "cpu" "mpccore"))
"mciu_mpc*6")
diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md
index f905a0d..73eac1f 100644
--- a/gcc/config/rs6000/power4.md
+++ b/gcc/config/rs6000/power4.md
@@ -314,12 +314,14 @@ (define_insn_reservation "power4-imul3" 4
; SPR move only executes in first IU.
; Integer division only executes in second IU.
(define_insn_reservation "power4-idiv" 36
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4,iu2_power4*35")
(define_insn_reservation "power4-ldiv" 68
- (and (eq_attr "type" "ldiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4,iu2_power4*67")
diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md
index 407ec71..8aa477a 100644
--- a/gcc/config/rs6000/power5.md
+++ b/gcc/config/rs6000/power5.md
@@ -255,12 +255,14 @@ (define_insn_reservation "power5-imul3" 4
; SPR move only executes in first IU.
; Integer division only executes in second IU.
(define_insn_reservation "power5-idiv" 36
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu2_power5*35")
(define_insn_reservation "power5-ldiv" 68
- (and (eq_attr "type" "ldiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu2_power5*67")
diff --git a/gcc/config/rs6000/power6.md b/gcc/config/rs6000/power6.md
index 3a77fc5..26e17f9 100644
--- a/gcc/config/rs6000/power6.md
+++ b/gcc/config/rs6000/power6.md
@@ -410,7 +410,8 @@ (define_bypass 9 "power6-imul,\
"store_data_bypass_p")
(define_insn_reservation "power6-idiv" 44
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power6"))
"(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\
|(iu1_power6*44+iu2_power6*44+fpu2_power6*44)");
@@ -425,7 +426,8 @@ (define_insn_reservation "power6-idiv" 44
; "store_data_bypass_p")
(define_insn_reservation "power6-ldiv" 56
- (and (eq_attr "type" "ldiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power6"))
"(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\
|(iu1_power6*56+iu2_power6*56+fpu2_power6*56)");
diff --git a/gcc/config/rs6000/power7.md b/gcc/config/rs6000/power7.md
index d6ddc24..5527829 100644
--- a/gcc/config/rs6000/power7.md
+++ b/gcc/config/rs6000/power7.md
@@ -219,12 +219,14 @@ (define_insn_reservation "power7-mul-compare" 5
"DU2F_power7,FXU_power7,nothing*3,FXU_power7")
(define_insn_reservation "power7-idiv" 36
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power7"))
"DU2F_power7,iu1_power7*36|iu2_power7*36")
(define_insn_reservation "power7-ldiv" 68
- (and (eq_attr "type" "ldiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power7"))
"DU2F_power7,iu1_power7*68|iu2_power7*68")
diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md
index f7bd9f8..99c9ec7 100644
--- a/gcc/config/rs6000/power8.md
+++ b/gcc/config/rs6000/power8.md
@@ -250,12 +250,14 @@ (define_bypass 7 "power8-mul,power8-mul-compare"
; FXU divides are not pipelined
(define_insn_reservation "power8-idiv" 37
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power8"))
"DU_any_power8,fxu0_power8*37|fxu1_power8*37")
(define_insn_reservation "power8-ldiv" 68
- (and (eq_attr "type" "ldiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power8"))
"DU_any_power8,fxu0_power8*68|fxu1_power8*68")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 8d9eb4d..1c432cd 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -26260,16 +26260,10 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
return 17;
break;
}
- case TYPE_IDIV:
+ case TYPE_DIV:
{
if (! store_data_bypass_p (dep_insn, insn))
- return 45;
- break;
- }
- case TYPE_LDIV:
- {
- if (! store_data_bypass_p (dep_insn, insn))
- return 57;
+ return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
break;
}
default:
@@ -26330,16 +26324,10 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
return 17;
break;
}
- case TYPE_IDIV:
- {
- if (set_to_load_agen (dep_insn, insn))
- return 45;
- break;
- }
- case TYPE_LDIV:
+ case TYPE_DIV:
{
if (set_to_load_agen (dep_insn, insn))
- return 57;
+ return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
break;
}
default:
@@ -26491,7 +26479,7 @@ is_cracked_insn (rtx insn)
|| type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
|| (type == TYPE_MUL
&& get_attr_dot (insn) == DOT_YES)
- || type == TYPE_IDIV || type == TYPE_LDIV
+ || type == TYPE_DIV
|| (type == TYPE_INSERT
&& get_attr_size (insn) == SIZE_32))
return true;
@@ -26648,7 +26636,7 @@ rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
break;
case TYPE_MUL:
- case TYPE_IDIV:
+ case TYPE_DIV:
fprintf (stderr, "priority was %#x (%d) before adjustment\n",
priority, priority);
if (priority >= 0 && priority < 0x01000000)
@@ -26702,8 +26690,7 @@ is_nonpipeline_insn (rtx insn)
type = get_attr_type (insn);
if (type == TYPE_MUL
- || type == TYPE_IDIV
- || type == TYPE_LDIV
+ || type == TYPE_DIV
|| type == TYPE_SDIV
|| type == TYPE_DDIV
|| type == TYPE_SSQRT
@@ -27302,8 +27289,7 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_CR_LOGICAL:
case TYPE_MTJMPR:
case TYPE_MFJMPR:
- case TYPE_IDIV:
- case TYPE_LDIV:
+ case TYPE_DIV:
case TYPE_LOAD_L:
case TYPE_STORE_C:
case TYPE_ISYNC:
@@ -27324,7 +27310,6 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_VAR_SHIFT_ROTATE:
case TYPE_TRAP:
case TYPE_MUL:
- case TYPE_IDIV:
case TYPE_INSERT:
case TYPE_DELAYED_COMPARE:
case TYPE_FPCOMPARE:
@@ -27337,6 +27322,11 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_LOAD_L:
case TYPE_STORE_C:
return true;
+ case TYPE_DIV:
+ if (get_attr_size (insn) == SIZE_32)
+ return true;
+ else
+ break;
case TYPE_LOAD:
case TYPE_STORE:
case TYPE_FPLOAD:
@@ -27358,8 +27348,7 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_MFCR:
case TYPE_MFCRF:
case TYPE_MTCR:
- case TYPE_IDIV:
- case TYPE_LDIV:
+ case TYPE_DIV:
case TYPE_COMPARE:
case TYPE_DELAYED_COMPARE:
case TYPE_VAR_DELAYED_COMPARE:
@@ -27468,7 +27457,6 @@ insn_must_be_last_in_group (rtx insn)
case TYPE_VAR_SHIFT_ROTATE:
case TYPE_TRAP:
case TYPE_MUL:
- case TYPE_IDIV:
case TYPE_DELAYED_COMPARE:
case TYPE_FPCOMPARE:
case TYPE_MFCR:
@@ -27480,6 +27468,11 @@ insn_must_be_last_in_group (rtx insn)
case TYPE_LOAD_L:
case TYPE_STORE_C:
return true;
+ case TYPE_DIV:
+ if (get_attr_size (insn) == SIZE_32)
+ return true;
+ else
+ break;
default:
break;
}
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 28410e7..0b13cfe 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -160,7 +160,7 @@ (define_c_enum "unspecv"
(define_attr "type"
"integer,two,three,
shift,var_shift_rotate,insert,
- mul,halfmul,idiv,ldiv,
+ mul,halfmul,div,
exts,cntlz,popcnt,isel,
load,store,fpload,fpstore,vecload,vecstore,
cmp,
@@ -423,6 +423,9 @@ (define_mode_attr wd [(QI "b")
(V4SI "w")
(V2DI "d")])
+;; How many bits in this mode?
+(define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")])
+
; DImode bits
(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
@@ -539,11 +542,6 @@ (define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X")
(V2DI "X,X,X,X,X")
(V2DF "X,X,X,X,X")
(V1TI "X,X,X,X,X")])
-
-;; Mode attribute to give the correct type for integer divides
-(define_mode_attr idiv_ldiv [(SI "idiv")
- (DI "ldiv")])
-
\f
;; Start with fixed-point load and store insns. Here we put only the more
;; complex forms. Basic data transfer is done later.
@@ -2747,7 +2745,8 @@ (define_insn "udiv<mode>3"
(match_operand:GPR 2 "gpc_reg_operand" "r")))]
""
"div<wd>u %0,%1,%2"
- [(set_attr "type" "<idiv_ldiv>")])
+ [(set_attr "type" "div")
+ (set_attr "size" "<bits>")])
;; For powers of two we can do srai/aze for divide and then adjust for
@@ -2771,7 +2770,8 @@ (define_insn "*div<mode>3"
(match_operand:GPR 2 "gpc_reg_operand" "r")))]
""
"div<wd> %0,%1,%2"
- [(set_attr "type" "<idiv_ldiv>")])
+ [(set_attr "type" "div")
+ (set_attr "size" "<bits>")])
(define_expand "mod<mode>3"
[(use (match_operand:GPR 0 "gpc_reg_operand" ""))
@@ -15507,7 +15507,8 @@ (define_insn "div<div_extend>_<mode>"
UNSPEC_DIV_EXTEND))]
"TARGET_POPCNTD"
"div<wd><div_extend> %0,%1,%2"
- [(set_attr "type" "<idiv_ldiv>")])
+ [(set_attr "type" "div")
+ (set_attr "size" "<bits>")])
\f
;; Pack/unpack 128-bit floating point types that take 2 scalar registers
diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md
index aaddb59..0260a1c 100644
--- a/gcc/config/rs6000/rs64.md
+++ b/gcc/config/rs6000/rs64.md
@@ -86,12 +86,14 @@ (define_insn_reservation "rs64a-lmul" 34
"mciu_rs64*34")
(define_insn_reservation "rs64a-idiv" 66
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "32")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*66")
(define_insn_reservation "rs64a-ldiv" 66
- (and (eq_attr "type" "ldiv")
+ (and (eq_attr "type" "div")
+ (eq_attr "size" "64")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*66")
diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md
index 6c7516d..1d33c0f 100644
--- a/gcc/config/rs6000/titan.md
+++ b/gcc/config/rs6000/titan.md
@@ -67,7 +67,7 @@ (define_insn_reservation "titan_fxu_shift_and_rotate" 2
;; through its latency and initial disptach bottlenecks (i.e. issue
;; slots and fxu scheduler availability)
(define_insn_reservation "titan_fxu_div" 34
- (and (eq_attr "type" "idiv")
+ (and (eq_attr "type" "div")
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh")
--
1.8.1.4
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 7/9] rs6000: Make all add instructions one type
2014-05-23 6:13 [PATCH 1/9] rs6000: Clean up the "type" attribute Segher Boessenkool
` (2 preceding siblings ...)
2014-05-23 6:13 ` [PATCH 3/9] rs6000: Make all multiply " Segher Boessenkool
@ 2014-05-23 6:56 ` Segher Boessenkool
2014-05-23 13:45 ` David Edelsohn
2014-05-23 6:56 ` [PATCH 8/9] rs6000: Make all logical " Segher Boessenkool
` (4 subsequent siblings)
8 siblings, 1 reply; 20+ messages in thread
From: Segher Boessenkool @ 2014-05-23 6:56 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
They are currently just "integer", but the dot version is fast_compare.
This makes them all "add". Later we should introduce attributes to
distinguish e.g. addc and adde (which aren't currently handled as
separate instructions at all, only in groups).
2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
gcc/
* config/rs6000/rs6000.md (type): Add "add".
(*add<mode>3_internal1, addsi3_high, *add<mode>3_internal2,
*add<mode>3_internal3, *neg<mode>2_internal, and 5 anonymous
define_insns): Use it.
* config/rs6000/rs6000.c (rs6000_adjust_cost): Adjust.
* config/rs6000/40x.md (ppc403-integer, ppc403-compare): Adjust.
* config/rs6000/440.md (ppc440-integer, ppc440-compare): Adjust.
* config/rs6000/476.md (ppc476-simple-integer, ppc476-compare):
Adjust.
* config/rs6000/601.md (ppc601-integer): Adjust.
* config/rs6000/603.md (ppc603-integer, ppc603-compare): Adjust.
* config/rs6000/6xx.md (ppc604-integer, ppc604-compare): Adjust.
* config/rs6000/7450.md (ppc7450-integer, ppc7450-compare): Adjust.
* config/rs6000/7xx.md (ppc750-integer, ppc750-compare): Adjust.
* config/rs6000/8540.md (ppc8540_su): Adjust.
* config/rs6000/cell.md (cell-integer, cell-fast-cmp,
cell-cmp-microcoded): Adjust.
* config/rs6000/e300c2c3.md (ppce300c3_cmp, ppce300c3_iu): Adjust.
* config/rs6000/e500mc.md (e500mc_su): Adjust.
* config/rs6000/e500mc64.md (e500mc64_su, e500mc64_su2): Adjust.
* config/rs6000/e5500.md (e5500_sfx, e5500_sfx2): Adjust.
* config/rs6000/e6500.md (e6500_sfx, e6500_sfx2): Adjust.
* config/rs6000/mpc.md (mpccore-integer, mpccore-compare): Adjust.
* config/rs6000/power4.md (power4-integer, power4-cmp): Adjust.
* config/rs6000/power5.md (power5-integer, power5-cmp): Adjust.
* config/rs6000/power6.md (power6-integer, power6-fast-compare):
Adjust.
* config/rs6000/power7.md (power7-integer, power7-cmp): Adjust.
* config/rs6000/power8.md (power8-1cyc, power8-fast-compare):
Adjust.
* config/rs6000/rs64.md (rs64a-integer, rs64a-compare): Adjust.
* config/rs6000/titan.md (titan_fxu_adder, titan_fxu_alu): Adjust.
---
gcc/config/rs6000/40x.md | 4 ++--
gcc/config/rs6000/440.md | 8 ++++++--
gcc/config/rs6000/476.md | 4 ++--
gcc/config/rs6000/601.md | 2 +-
gcc/config/rs6000/603.md | 4 ++--
gcc/config/rs6000/6xx.md | 4 ++--
gcc/config/rs6000/7450.md | 4 ++--
gcc/config/rs6000/7xx.md | 4 ++--
gcc/config/rs6000/8540.md | 2 +-
gcc/config/rs6000/cell.md | 6 +++---
gcc/config/rs6000/e300c2c3.md | 6 ++++--
gcc/config/rs6000/e500mc.md | 2 +-
gcc/config/rs6000/e500mc64.md | 4 ++++
gcc/config/rs6000/e5500.md | 6 +++++-
gcc/config/rs6000/e6500.md | 6 +++++-
gcc/config/rs6000/mpc.md | 4 ++--
gcc/config/rs6000/power4.md | 6 ++++--
gcc/config/rs6000/power5.md | 6 ++++--
gcc/config/rs6000/power6.md | 8 ++++++--
gcc/config/rs6000/power7.md | 6 ++++--
gcc/config/rs6000/power8.md | 6 ++++--
gcc/config/rs6000/rs6000.c | 2 ++
gcc/config/rs6000/rs6000.md | 30 +++++++++++++++++++-----------
gcc/config/rs6000/rs64.md | 4 ++--
gcc/config/rs6000/titan.md | 8 ++++++--
25 files changed, 95 insertions(+), 51 deletions(-)
diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md
index 30ac01d..85b9e41 100644
--- a/gcc/config/rs6000/40x.md
+++ b/gcc/config/rs6000/40x.md
@@ -37,7 +37,7 @@ (define_insn_reservation "ppc403-store" 2
(define_insn_reservation "ppc403-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
@@ -54,7 +54,7 @@ (define_insn_reservation "ppc403-three" 1
(define_insn_reservation "ppc403-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,nothing,bpu_40x")
diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md
index 3a36ffb..23f69b1 100644
--- a/gcc/config/rs6000/440.md
+++ b/gcc/config/rs6000/440.md
@@ -53,7 +53,9 @@ (define_insn_reservation "ppc440-fpstore" 3
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1
- (and (eq_attr "type" "integer,insert,shift,trap,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert,shift,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
@@ -93,7 +95,9 @@ (define_insn_reservation "ppc440-branch" 1
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-compare" 2
- (and (eq_attr "type" "cmp,fast_compare,compare,cr_logical,delayed_cr,mfcr")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare,cr_logical,delayed_cr,mfcr")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md
index 41cd247..dd39bc2 100644
--- a/gcc/config/rs6000/476.md
+++ b/gcc/config/rs6000/476.md
@@ -64,7 +64,7 @@ (define_insn_reservation "ppc476-fpstore" 4
(define_insn_reservation "ppc476-simple-integer" 1
(and (ior (eq_attr "type" "integer,insert,exts")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
@@ -79,7 +79,7 @@ (define_insn_reservation "ppc476-complex-integer" 1
(define_insn_reservation "ppc476-compare" 4
(and (ior (eq_attr "type" "compare,fast_compare,mfcr,mfcrf,\
mtcr,mfjmpr,mtjmpr")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
diff --git a/gcc/config/rs6000/601.md b/gcc/config/rs6000/601.md
index f6eca7d..e8207a8 100644
--- a/gcc/config/rs6000/601.md
+++ b/gcc/config/rs6000/601.md
@@ -45,7 +45,7 @@ (define_insn_reservation "ppc601-fpstore" 3
"iu_ppc601+fpu_ppc601")
(define_insn_reservation "ppc601-integer" 1
- (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,add,insert,trap,cntlz,exts,isel")
(and (eq_attr "type" "shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc601"))
diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md
index f64f428..0db3f42 100644
--- a/gcc/config/rs6000/603.md
+++ b/gcc/config/rs6000/603.md
@@ -59,7 +59,7 @@ (define_insn_reservation "ppc603-storec" 8
(define_insn_reservation "ppc603-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc603"))
"iu_603")
@@ -94,7 +94,7 @@ (define_insn_reservation "ppc603-idiv" 37
(define_insn_reservation "ppc603-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc603"))
"iu_603,nothing,bpu_603")
diff --git a/gcc/config/rs6000/6xx.md b/gcc/config/rs6000/6xx.md
index 6d4ccb7..fc9d857 100644
--- a/gcc/config/rs6000/6xx.md
+++ b/gcc/config/rs6000/6xx.md
@@ -74,7 +74,7 @@ (define_insn_reservation "ppc630-llsc" 4
(define_insn_reservation "ppc604-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
@@ -148,7 +148,7 @@ (define_insn_reservation "ppc620-ldiv" 37
(define_insn_reservation "ppc604-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"(iu1_6xx|iu2_6xx)")
diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md
index 39815e9..3c75d05 100644
--- a/gcc/config/rs6000/7450.md
+++ b/gcc/config/rs6000/7450.md
@@ -74,7 +74,7 @@ (define_insn_reservation "ppc7450-sync" 35
(define_insn_reservation "ppc7450-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
@@ -109,7 +109,7 @@ (define_insn_reservation "ppc7450-idiv" 23
(define_insn_reservation "ppc7450-compare" 2
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md
index f9a9fb8..89de8df 100644
--- a/gcc/config/rs6000/7xx.md
+++ b/gcc/config/rs6000/7xx.md
@@ -62,7 +62,7 @@ (define_insn_reservation "ppc750-storec" 8
(define_insn_reservation "ppc750-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx")
@@ -102,7 +102,7 @@ (define_insn_reservation "ppc750-idiv" 19
(define_insn_reservation "ppc750-compare" 2
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,(iu1_7xx|iu2_7xx)")
diff --git a/gcc/config/rs6000/8540.md b/gcc/config/rs6000/8540.md
index fccddfe..22a67d0 100644
--- a/gcc/config/rs6000/8540.md
+++ b/gcc/config/rs6000/8540.md
@@ -84,7 +84,7 @@ (define_reservation "ppc8540_su_stage0"
;; Simple SU insns
(define_insn_reservation "ppc8540_su" 1
- (and (eq_attr "type" "integer,insert,cmp,compare,fast_compare,\
+ (and (eq_attr "type" "integer,add,insert,cmp,compare,fast_compare,\
shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md
index 923524d..70af72b 100644
--- a/gcc/config/rs6000/cell.md
+++ b/gcc/config/rs6000/cell.md
@@ -167,7 +167,7 @@ (define_insn_reservation "cell-vecstore" 1
;; Integer latency is 2 cycles
(define_insn_reservation "cell-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
@@ -202,7 +202,7 @@ (define_insn_reservation "cell-cmp" 1
;; add, addo, sub, subo, alter cr0, rldcli, rlwinm
(define_insn_reservation "cell-fast-cmp" 2
(and (ior (eq_attr "type" "fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "cell")
(eq_attr "cell_micro" "not"))
@@ -210,7 +210,7 @@ (define_insn_reservation "cell-fast-cmp" 2
(define_insn_reservation "cell-cmp-microcoded" 9
(and (ior (eq_attr "type" "fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "cell")
(eq_attr "cell_micro" "always"))
diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md
index 26a449d..ccc8cc3 100644
--- a/gcc/config/rs6000/e300c2c3.md
+++ b/gcc/config/rs6000/e300c2c3.md
@@ -84,7 +84,7 @@ (define_reservation "ppce300c3_iu_stage0"
;; Compares can be executed either one of the IU or SRU
(define_insn_reservation "ppce300c3_cmp" 1
(and (ior (eq_attr "type" "cmp,compare,fast_compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
@@ -92,7 +92,9 @@ (define_insn_reservation "ppce300c3_cmp" 1
;; Other one cycle IU insns
(define_insn_reservation "ppce300c3_iu" 1
- (and (eq_attr "type" "integer,insert,isel")
+ (and (ior (eq_attr "type" "integer,insert,isel")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
diff --git a/gcc/config/rs6000/e500mc.md b/gcc/config/rs6000/e500mc.md
index 834e0d2..c4c84c6 100644
--- a/gcc/config/rs6000/e500mc.md
+++ b/gcc/config/rs6000/e500mc.md
@@ -70,7 +70,7 @@ (define_reservation "e500mc_su_stage0"
;; Simple SU insns.
(define_insn_reservation "e500mc_su" 1
- (and (eq_attr "type" "integer,insert,cmp,compare,fast_compare,\
+ (and (eq_attr "type" "integer,add,insert,cmp,compare,fast_compare,\
shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
diff --git a/gcc/config/rs6000/e500mc64.md b/gcc/config/rs6000/e500mc64.md
index 026d016..70ee18e 100644
--- a/gcc/config/rs6000/e500mc64.md
+++ b/gcc/config/rs6000/e500mc64.md
@@ -70,6 +70,8 @@ (define_reservation "e500mc64_su_stage0"
;; Simple SU insns.
(define_insn_reservation "e500mc64_su" 1
(and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "no")
(eq_attr "var_shift" "no")))
@@ -78,6 +80,8 @@ (define_insn_reservation "e500mc64_su" 1
(define_insn_reservation "e500mc64_su2" 2
(and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "yes")
(eq_attr "var_shift" "no")))
diff --git a/gcc/config/rs6000/e5500.md b/gcc/config/rs6000/e5500.md
index edd0ef5..6ca86d7 100644
--- a/gcc/config/rs6000/e5500.md
+++ b/gcc/config/rs6000/e5500.md
@@ -57,13 +57,17 @@ (define_reservation "e5500_sfx"
;; SFX.
(define_insn_reservation "e5500_sfx" 1
(and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
(define_insn_reservation "e5500_sfx2" 2
- (and (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md
index 609d564..15dfc9c 100644
--- a/gcc/config/rs6000/e6500.md
+++ b/gcc/config/rs6000/e6500.md
@@ -60,13 +60,17 @@ (define_reservation "e6500_sfx"
;; SFX.
(define_insn_reservation "e6500_sfx" 1
(and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
(define_insn_reservation "e6500_sfx2" 2
- (and (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md
index f83c752..ffcb7a7 100644
--- a/gcc/config/rs6000/mpc.md
+++ b/gcc/config/rs6000/mpc.md
@@ -42,7 +42,7 @@ (define_insn_reservation "mpccore-fpload" 2
(define_insn_reservation "mpccore-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "mpccore"))
"iu_mpc")
@@ -70,7 +70,7 @@ (define_insn_reservation "mpccore-idiv" 6
(define_insn_reservation "mpccore-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "mpccore"))
"iu_mpc,nothing,bpu_mpc")
diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md
index 6a1c108..cea473d 100644
--- a/gcc/config/rs6000/power4.md
+++ b/gcc/config/rs6000/power4.md
@@ -211,7 +211,7 @@ (define_insn_reservation "power4-llsc" 11
; Integer latency is 2 cycles
(define_insn_reservation "power4-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
@@ -250,7 +250,9 @@ (define_insn_reservation "power4-insert" 4
|(iu2_power4,nothing,iu1_power4))")
(define_insn_reservation "power4-cmp" 3
- (and (eq_attr "type" "cmp,fast_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power4"))
"iq_power4")
diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md
index 4ebb6cf..5df009e 100644
--- a/gcc/config/rs6000/power5.md
+++ b/gcc/config/rs6000/power5.md
@@ -167,7 +167,7 @@ (define_insn_reservation "power5-llsc" 11
; Integer latency is 2 cycles
(define_insn_reservation "power5-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel,popcnt")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
@@ -203,7 +203,9 @@ (define_insn_reservation "power5-insert" 4
"du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
(define_insn_reservation "power5-cmp" 3
- (and (eq_attr "type" "cmp,fast_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power5"))
"iq_power5")
diff --git a/gcc/config/rs6000/power6.md b/gcc/config/rs6000/power6.md
index b659645..9dfd39d 100644
--- a/gcc/config/rs6000/power6.md
+++ b/gcc/config/rs6000/power6.md
@@ -222,7 +222,9 @@ (define_insn_reservation "power6-sync" 11 ; N/A
"LSU_power6")
(define_insn_reservation "power6-integer" 1
- (and (eq_attr "type" "integer")
+ (and (ior (eq_attr "type" "integer")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "power6"))
"FXU_power6")
@@ -336,7 +338,9 @@ (define_insn_reservation "power6-compare" 1
"FXU_power6")
(define_insn_reservation "power6-fast-compare" 1
- (and (eq_attr "type" "fast_compare")
+ (and (ior (eq_attr "type" "fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power6"))
"FXU_power6")
diff --git a/gcc/config/rs6000/power7.md b/gcc/config/rs6000/power7.md
index f4bd0b8..00aa26b 100644
--- a/gcc/config/rs6000/power7.md
+++ b/gcc/config/rs6000/power7.md
@@ -175,7 +175,7 @@ (define_insn_reservation "power7-sync" 11
; FX Unit
(define_insn_reservation "power7-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,exts,isel,popcnt")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
@@ -196,7 +196,9 @@ (define_insn_reservation "power7-three" 3
"DU_power7+DU_power7+DU_power7,FXU_power7,FXU_power7,FXU_power7")
(define_insn_reservation "power7-cmp" 1
- (and (eq_attr "type" "cmp,fast_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md
index 2d50d4a..b2eeac4 100644
--- a/gcc/config/rs6000/power8.md
+++ b/gcc/config/rs6000/power8.md
@@ -169,7 +169,7 @@ (define_insn_reservation "power8-sync" 1
; FX Unit
(define_insn_reservation "power8-1cyc" 1
(and (ior (eq_attr "type" "integer,insert,trap,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
@@ -207,7 +207,9 @@ (define_insn_reservation "power8-cmp" 2
; fast_compare : add./and./nor./etc
(define_insn_reservation "power8-fast-compare" 2
- (and (eq_attr "type" "fast_compare")
+ (and (ior (eq_attr "type" "fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index fb3c189..c4f4df2 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -26240,6 +26240,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
break;
}
case TYPE_INTEGER:
+ case TYPE_ADD:
case TYPE_COMPARE:
case TYPE_FAST_COMPARE:
case TYPE_EXTS:
@@ -26303,6 +26304,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
break;
}
case TYPE_INTEGER:
+ case TYPE_ADD:
case TYPE_COMPARE:
case TYPE_FAST_COMPARE:
case TYPE_EXTS:
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 67113ee..3f6cefd 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -159,7 +159,7 @@ (define_c_enum "unspecv"
;; computations.
(define_attr "type"
"integer,two,three,
- shift,insert,
+ add,shift,insert,
mul,halfmul,div,
exts,cntlz,popcnt,isel,
load,store,fpload,fpstore,vecload,vecstore,
@@ -1820,7 +1820,7 @@ (define_insn "*add<mode>3_internal1"
addi %0,%1,%2
addic %0,%1,%2
addis %0,%1,%v2"
- [(set_attr "length" "4,4,4,4")])
+ [(set_attr "type" "add")])
(define_insn "addsi3_high"
[(set (match_operand:SI 0 "gpc_reg_operand" "=b")
@@ -1828,7 +1828,7 @@ (define_insn "addsi3_high"
(high:SI (match_operand 2 "" ""))))]
"TARGET_MACHO && !TARGET_64BIT"
"addis %0,%1,ha16(%2)"
- [(set_attr "length" "4")])
+ [(set_attr "type" "add")])
(define_insn "*add<mode>3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -1842,7 +1842,8 @@ (define_insn "*add<mode>3_internal2"
addic. %3,%1,%2
#
#"
- [(set_attr "type" "fast_compare,compare,compare,compare")
+ [(set_attr "type" "add,compare,compare,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -1874,7 +1875,8 @@ (define_insn "*add<mode>3_internal3"
addic. %0,%1,%2
#
#"
- [(set_attr "type" "fast_compare,compare,compare,compare")
+ [(set_attr "type" "add,compare,compare,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -2000,7 +2002,8 @@ (define_insn ""
""
"@
subf %0,%2,%1
- subfic %0,%2,%1")
+ subfic %0,%2,%1"
+ [(set_attr "type" "add")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -2012,7 +2015,8 @@ (define_insn ""
"@
subf. %3,%2,%1
#"
- [(set_attr "type" "fast_compare")
+ [(set_attr "type" "add")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -2042,7 +2046,8 @@ (define_insn ""
"@
subf. %0,%2,%1
#"
- [(set_attr "type" "fast_compare")
+ [(set_attr "type" "add")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -2087,7 +2092,8 @@ (define_insn "*neg<mode>2_internal"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
""
- "neg %0,%1")
+ "neg %0,%1"
+ [(set_attr "type" "add")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -2098,7 +2104,8 @@ (define_insn ""
"@
neg. %2,%1
#"
- [(set_attr "type" "fast_compare")
+ [(set_attr "type" "add")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -2124,7 +2131,8 @@ (define_insn ""
"@
neg. %0,%1
#"
- [(set_attr "type" "fast_compare")
+ [(set_attr "type" "add")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md
index 82ace4a..2c32415 100644
--- a/gcc/config/rs6000/rs64.md
+++ b/gcc/config/rs6000/rs64.md
@@ -47,7 +47,7 @@ (define_insn_reservation "rs64a-llsc" 2
(define_insn_reservation "rs64a-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "rs64a"))
"iu_rs64")
@@ -100,7 +100,7 @@ (define_insn_reservation "rs64a-ldiv" 66
(define_insn_reservation "rs64a-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "rs64a"))
"iu_rs64,nothing,bpu_rs64")
diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md
index 7443d7c..cb284ff 100644
--- a/gcc/config/rs6000/titan.md
+++ b/gcc/config/rs6000/titan.md
@@ -34,7 +34,9 @@ (define_cpu_unit "titan_fxu_sh,titan_fxu_wb" "titan_fxu")
;; instructions. It provides its own, dedicated result-bus, so we
;; don't need the titan_fxu_wb reservation to complete.
(define_insn_reservation "titan_fxu_adder" 1
- (and (eq_attr "type" "cmp,fast_compare,trap")
+ (and (ior (eq_attr "type" "cmp,fast_compare,trap")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh")
@@ -72,7 +74,9 @@ (define_insn_reservation "titan_fxu_div" 34
"titan_issue,titan_fxu_sh")
(define_insn_reservation "titan_fxu_alu" 1
- (and (eq_attr "type" "integer,exts")
+ (and (ior (eq_attr "type" "integer,exts")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing,titan_fxu_wb")
--
1.8.1.4
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 8/9] rs6000: Make all logical instructions one type
2014-05-23 6:13 [PATCH 1/9] rs6000: Clean up the "type" attribute Segher Boessenkool
` (3 preceding siblings ...)
2014-05-23 6:56 ` [PATCH 7/9] rs6000: Make all add " Segher Boessenkool
@ 2014-05-23 6:56 ` Segher Boessenkool
2014-05-23 13:46 ` David Edelsohn
2014-05-23 6:56 ` [PATCH 5/9] rs6000: Make all divide " Segher Boessenkool
` (3 subsequent siblings)
8 siblings, 1 reply; 20+ messages in thread
From: Segher Boessenkool @ 2014-05-23 6:56 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
They are currently just "integer", but the dot version is fast_compare.
This makes them all "logical".
2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
gcc/
* config/rs6000/rs6000.md (type): Add "logical". Delete
"fast_compare".
(dot): Adjust comment.
(andsi3_mc, *andsi3_internal2_mc, *andsi3_internal3_mc,
*andsi3_internal4, *andsi3_internal5_mc, *boolsi3_internal2,
*boolsi3_internal3, *boolccsi3_internal2, *boolccsi3_internal3,
anddi3_mc, *anddi3_internal2_mc, *anddi3_internal3_mc,
*booldi3_internal2, *booldi3_internal3, *boolcdi3_internal2,
*boolcdi3_internal3, *boolccdi3_internal2, *boolccdi3_internal3,
*mov<mode>_internal2, and 10 anonymous define_insns): Use
"logical".
* config/rs6000/rs6000.c (rs6000_adjust_cost): Adjust.
* config/rs6000/40x.md: (ppc403-integer, ppc403-compare): Adjust.
* config/rs6000/440.md: (ppc440-integer, ppc440-compare): Adjust.
* config/rs6000/476.md: (ppc476-simple-integer, ppc476-compare):
Adjust.
* config/rs6000/603.md: (ppc603-integer, ppc603-compare): Adjust.
* config/rs6000/6xx.md: (ppc604-integer, ppc604-compare): Adjust.
* config/rs6000/7450.md: (ppc7450-integer, ppc7450-compare):
Adjust.
* config/rs6000/7xx.md: (ppc750-integer, ppc750-compare): Adjust.
* config/rs6000/8540.md: (ppc8540_su): Adjust.
* config/rs6000/cell.md: (cell-integer, cell-fast-cmp,
cell-cmp-microcoded): Adjust.
* config/rs6000/e300c2c3.md: (ppce300c3_cmp, ppce300c3_iu):
Adjust.
* config/rs6000/e500mc.md: (e500mc_su): Adjust.
* config/rs6000/e500mc64.md: (e500mc64_su, e500mc64_su2): Adjust.
* config/rs6000/e5500.md: (e5500_sfx, e5500_sfx2): Adjust.
* config/rs6000/e6500.md: (e6500_sfx, e6500_sfx2): Adjust.
* config/rs6000/mpc.md: (mpccore-integer, mpccore-compare):
Adjust.
* config/rs6000/power4.md: (power4-integer, power4-cmp): Adjust.
* config/rs6000/power5.md: (power5-integer, power5-cmp): Adjust.
* config/rs6000/power6.md: (power6-integer, power6-fast-compare):
Adjust.
* config/rs6000/power7.md: (power7-integer, power7-cmp): Adjust.
* config/rs6000/power8.md: (power8-1cyc, power8-fast-compare):
Adjust. Adjust comment.
* config/rs6000/rs64.md: (rs64a-integer, rs64a-compare): Adjust.
* config/rs6000/titan.md: (titan_fxu_adder, titan_fxu_alu):
Adjust.
---
gcc/config/rs6000/40x.md | 6 +--
gcc/config/rs6000/440.md | 6 +--
gcc/config/rs6000/476.md | 7 ++--
gcc/config/rs6000/603.md | 6 +--
gcc/config/rs6000/6xx.md | 6 +--
gcc/config/rs6000/7450.md | 6 +--
gcc/config/rs6000/7xx.md | 6 +--
gcc/config/rs6000/8540.md | 2 +-
gcc/config/rs6000/cell.md | 10 ++---
gcc/config/rs6000/e300c2c3.md | 6 +--
gcc/config/rs6000/e500mc.md | 2 +-
gcc/config/rs6000/e500mc64.md | 6 +--
gcc/config/rs6000/e5500.md | 6 +--
gcc/config/rs6000/e6500.md | 6 +--
gcc/config/rs6000/mpc.md | 6 +--
gcc/config/rs6000/power4.md | 6 +--
gcc/config/rs6000/power5.md | 6 +--
gcc/config/rs6000/power6.md | 7 ++--
gcc/config/rs6000/power7.md | 6 +--
gcc/config/rs6000/power8.md | 9 ++---
gcc/config/rs6000/rs6000.c | 4 +-
gcc/config/rs6000/rs6000.md | 89 ++++++++++++++++++++++++++-----------------
gcc/config/rs6000/rs64.md | 6 +--
gcc/config/rs6000/titan.md | 6 +--
24 files changed, 122 insertions(+), 104 deletions(-)
diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md
index 85b9e41..b29e06a 100644
--- a/gcc/config/rs6000/40x.md
+++ b/gcc/config/rs6000/40x.md
@@ -37,7 +37,7 @@ (define_insn_reservation "ppc403-store" 2
(define_insn_reservation "ppc403-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "add,shift")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
@@ -53,8 +53,8 @@ (define_insn_reservation "ppc403-three" 1
"iu_40x,iu_40x,iu_40x")
(define_insn_reservation "ppc403-compare" 3
- (and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "add,shift")
+ (and (ior (eq_attr "type" "cmp,compare")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,nothing,bpu_40x")
diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md
index 23f69b1..bc8da3e 100644
--- a/gcc/config/rs6000/440.md
+++ b/gcc/config/rs6000/440.md
@@ -54,7 +54,7 @@ (define_insn_reservation "ppc440-fpstore" 3
(define_insn_reservation "ppc440-integer" 1
(and (ior (eq_attr "type" "integer,insert,shift,trap,cntlz,exts,isel")
- (and (eq_attr "type" "add")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
@@ -95,8 +95,8 @@ (define_insn_reservation "ppc440-branch" 1
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-compare" 2
- (and (ior (eq_attr "type" "cmp,fast_compare,compare,cr_logical,delayed_cr,mfcr")
- (and (eq_attr "type" "add")
+ (and (ior (eq_attr "type" "cmp,compare,cr_logical,delayed_cr,mfcr")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md
index dd39bc2..4c879f4 100644
--- a/gcc/config/rs6000/476.md
+++ b/gcc/config/rs6000/476.md
@@ -64,7 +64,7 @@ (define_insn_reservation "ppc476-fpstore" 4
(define_insn_reservation "ppc476-simple-integer" 1
(and (ior (eq_attr "type" "integer,insert,exts")
- (and (eq_attr "type" "add,shift")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
@@ -77,9 +77,8 @@ (define_insn_reservation "ppc476-complex-integer" 1
ppc476_i_pipe")
(define_insn_reservation "ppc476-compare" 4
- (and (ior (eq_attr "type" "compare,fast_compare,mfcr,mfcrf,\
- mtcr,mfjmpr,mtjmpr")
- (and (eq_attr "type" "add,shift")
+ (and (ior (eq_attr "type" "compare,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md
index 0db3f42..871957a 100644
--- a/gcc/config/rs6000/603.md
+++ b/gcc/config/rs6000/603.md
@@ -59,7 +59,7 @@ (define_insn_reservation "ppc603-storec" 8
(define_insn_reservation "ppc603-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "add,shift")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc603"))
"iu_603")
@@ -93,8 +93,8 @@ (define_insn_reservation "ppc603-idiv" 37
"iu_603*37")
(define_insn_reservation "ppc603-compare" 3
- (and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "add,shift")
+ (and (ior (eq_attr "type" "cmp,compare")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc603"))
"iu_603,nothing,bpu_603")
diff --git a/gcc/config/rs6000/6xx.md b/gcc/config/rs6000/6xx.md
index fc9d857..9d6ba05 100644
--- a/gcc/config/rs6000/6xx.md
+++ b/gcc/config/rs6000/6xx.md
@@ -74,7 +74,7 @@ (define_insn_reservation "ppc630-llsc" 4
(define_insn_reservation "ppc604-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "add,shift")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
@@ -147,8 +147,8 @@ (define_insn_reservation "ppc620-ldiv" 37
"mciu_6xx*36")
(define_insn_reservation "ppc604-compare" 3
- (and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "add,shift")
+ (and (ior (eq_attr "type" "cmp,compare")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"(iu1_6xx|iu2_6xx)")
diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md
index 3c75d05..4271efa 100644
--- a/gcc/config/rs6000/7450.md
+++ b/gcc/config/rs6000/7450.md
@@ -74,7 +74,7 @@ (define_insn_reservation "ppc7450-sync" 35
(define_insn_reservation "ppc7450-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "add,shift")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
@@ -108,8 +108,8 @@ (define_insn_reservation "ppc7450-idiv" 23
"ppc7450_du,mciu_7450*23")
(define_insn_reservation "ppc7450-compare" 2
- (and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "add,shift")
+ (and (ior (eq_attr "type" "cmp,compare")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md
index 89de8df..aba4a77 100644
--- a/gcc/config/rs6000/7xx.md
+++ b/gcc/config/rs6000/7xx.md
@@ -62,7 +62,7 @@ (define_insn_reservation "ppc750-storec" 8
(define_insn_reservation "ppc750-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "add,shift")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx")
@@ -101,8 +101,8 @@ (define_insn_reservation "ppc750-idiv" 19
"ppc750_du,iu1_7xx*19")
(define_insn_reservation "ppc750-compare" 2
- (and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "add,shift")
+ (and (ior (eq_attr "type" "cmp,compare")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,(iu1_7xx|iu2_7xx)")
diff --git a/gcc/config/rs6000/8540.md b/gcc/config/rs6000/8540.md
index 22a67d0..90a3d27 100644
--- a/gcc/config/rs6000/8540.md
+++ b/gcc/config/rs6000/8540.md
@@ -84,7 +84,7 @@ (define_reservation "ppc8540_su_stage0"
;; Simple SU insns
(define_insn_reservation "ppc8540_su" 1
- (and (eq_attr "type" "integer,add,insert,cmp,compare,fast_compare,\
+ (and (eq_attr "type" "integer,add,logical,insert,cmp,compare,\
shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md
index 70af72b..b37cdba 100644
--- a/gcc/config/rs6000/cell.md
+++ b/gcc/config/rs6000/cell.md
@@ -167,7 +167,7 @@ (define_insn_reservation "cell-vecstore" 1
;; Integer latency is 2 cycles
(define_insn_reservation "cell-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
- (and (eq_attr "type" "add,shift")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
@@ -201,16 +201,16 @@ (define_insn_reservation "cell-cmp" 1
;; add, addo, sub, subo, alter cr0, rldcli, rlwinm
(define_insn_reservation "cell-fast-cmp" 2
- (and (ior (eq_attr "type" "fast_compare,compare")
- (and (eq_attr "type" "add,shift")
+ (and (ior (eq_attr "type" "compare")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "cell")
(eq_attr "cell_micro" "not"))
"slot01,fxu_cell")
(define_insn_reservation "cell-cmp-microcoded" 9
- (and (ior (eq_attr "type" "fast_compare,compare")
- (and (eq_attr "type" "add,shift")
+ (and (ior (eq_attr "type" "compare")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "cell")
(eq_attr "cell_micro" "always"))
diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md
index ccc8cc3..6ac585b 100644
--- a/gcc/config/rs6000/e300c2c3.md
+++ b/gcc/config/rs6000/e300c2c3.md
@@ -83,8 +83,8 @@ (define_reservation "ppce300c3_iu_stage0"
;; Compares can be executed either one of the IU or SRU
(define_insn_reservation "ppce300c3_cmp" 1
- (and (ior (eq_attr "type" "cmp,compare,fast_compare")
- (and (eq_attr "type" "add,shift")
+ (and (ior (eq_attr "type" "cmp,compare")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "yes")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
@@ -93,7 +93,7 @@ (define_insn_reservation "ppce300c3_cmp" 1
;; Other one cycle IU insns
(define_insn_reservation "ppce300c3_iu" 1
(and (ior (eq_attr "type" "integer,insert,isel")
- (and (eq_attr "type" "add")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "no")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
diff --git a/gcc/config/rs6000/e500mc.md b/gcc/config/rs6000/e500mc.md
index c4c84c6..2af7eb4 100644
--- a/gcc/config/rs6000/e500mc.md
+++ b/gcc/config/rs6000/e500mc.md
@@ -70,7 +70,7 @@ (define_reservation "e500mc_su_stage0"
;; Simple SU insns.
(define_insn_reservation "e500mc_su" 1
- (and (eq_attr "type" "integer,add,insert,cmp,compare,fast_compare,\
+ (and (eq_attr "type" "integer,add,logical,insert,cmp,compare,\
shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
diff --git a/gcc/config/rs6000/e500mc64.md b/gcc/config/rs6000/e500mc64.md
index 70ee18e..4582334 100644
--- a/gcc/config/rs6000/e500mc64.md
+++ b/gcc/config/rs6000/e500mc64.md
@@ -70,7 +70,7 @@ (define_reservation "e500mc64_su_stage0"
;; Simple SU insns.
(define_insn_reservation "e500mc64_su" 1
(and (ior (eq_attr "type" "integer,insert,cntlz,exts")
- (and (eq_attr "type" "add")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "no")
@@ -79,8 +79,8 @@ (define_insn_reservation "e500mc64_su" 1
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
(define_insn_reservation "e500mc64_su2" 2
- (and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
- (and (eq_attr "type" "add")
+ (and (ior (eq_attr "type" "cmp,compare,trap")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "yes")
diff --git a/gcc/config/rs6000/e5500.md b/gcc/config/rs6000/e5500.md
index 6ca86d7..49a5c39 100644
--- a/gcc/config/rs6000/e5500.md
+++ b/gcc/config/rs6000/e5500.md
@@ -57,7 +57,7 @@ (define_reservation "e5500_sfx"
;; SFX.
(define_insn_reservation "e5500_sfx" 1
(and (ior (eq_attr "type" "integer,insert,cntlz,exts")
- (and (eq_attr "type" "add")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "no")))
@@ -65,8 +65,8 @@ (define_insn_reservation "e5500_sfx" 1
"e5500_decode,e5500_sfx")
(define_insn_reservation "e5500_sfx2" 2
- (and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
- (and (eq_attr "type" "add")
+ (and (ior (eq_attr "type" "cmp,compare,trap")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md
index 15dfc9c..deec34b 100644
--- a/gcc/config/rs6000/e6500.md
+++ b/gcc/config/rs6000/e6500.md
@@ -60,7 +60,7 @@ (define_reservation "e6500_sfx"
;; SFX.
(define_insn_reservation "e6500_sfx" 1
(and (ior (eq_attr "type" "integer,insert,cntlz,exts")
- (and (eq_attr "type" "add")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "no")))
@@ -68,8 +68,8 @@ (define_insn_reservation "e6500_sfx" 1
"e6500_decode,e6500_sfx")
(define_insn_reservation "e6500_sfx2" 2
- (and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
- (and (eq_attr "type" "add")
+ (and (ior (eq_attr "type" "cmp,compare,trap")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md
index ffcb7a7..2f11a86 100644
--- a/gcc/config/rs6000/mpc.md
+++ b/gcc/config/rs6000/mpc.md
@@ -42,7 +42,7 @@ (define_insn_reservation "mpccore-fpload" 2
(define_insn_reservation "mpccore-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "add,shift")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "mpccore"))
"iu_mpc")
@@ -69,8 +69,8 @@ (define_insn_reservation "mpccore-idiv" 6
"mciu_mpc*6")
(define_insn_reservation "mpccore-compare" 3
- (and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "add,shift")
+ (and (ior (eq_attr "type" "cmp,compare")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "mpccore"))
"iu_mpc,nothing,bpu_mpc")
diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md
index cea473d..e46914e 100644
--- a/gcc/config/rs6000/power4.md
+++ b/gcc/config/rs6000/power4.md
@@ -211,7 +211,7 @@ (define_insn_reservation "power4-llsc" 11
; Integer latency is 2 cycles
(define_insn_reservation "power4-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
- (and (eq_attr "type" "add,shift")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
@@ -250,8 +250,8 @@ (define_insn_reservation "power4-insert" 4
|(iu2_power4,nothing,iu1_power4))")
(define_insn_reservation "power4-cmp" 3
- (and (ior (eq_attr "type" "cmp,fast_compare")
- (and (eq_attr "type" "add")
+ (and (ior (eq_attr "type" "cmp")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "power4"))
"iq_power4")
diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md
index 5df009e..198db82 100644
--- a/gcc/config/rs6000/power5.md
+++ b/gcc/config/rs6000/power5.md
@@ -167,7 +167,7 @@ (define_insn_reservation "power5-llsc" 11
; Integer latency is 2 cycles
(define_insn_reservation "power5-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel,popcnt")
- (and (eq_attr "type" "add,shift")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
@@ -203,8 +203,8 @@ (define_insn_reservation "power5-insert" 4
"du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
(define_insn_reservation "power5-cmp" 3
- (and (ior (eq_attr "type" "cmp,fast_compare")
- (and (eq_attr "type" "add")
+ (and (ior (eq_attr "type" "cmp")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "power5"))
"iq_power5")
diff --git a/gcc/config/rs6000/power6.md b/gcc/config/rs6000/power6.md
index 9dfd39d..e4a82a2 100644
--- a/gcc/config/rs6000/power6.md
+++ b/gcc/config/rs6000/power6.md
@@ -223,7 +223,7 @@ (define_insn_reservation "power6-sync" 11 ; N/A
(define_insn_reservation "power6-integer" 1
(and (ior (eq_attr "type" "integer")
- (and (eq_attr "type" "add")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power6"))
"FXU_power6")
@@ -338,9 +338,8 @@ (define_insn_reservation "power6-compare" 1
"FXU_power6")
(define_insn_reservation "power6-fast-compare" 1
- (and (ior (eq_attr "type" "fast_compare")
- (and (eq_attr "type" "add")
- (eq_attr "dot" "yes")))
+ (and (eq_attr "type" "add,logical")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "power6"))
"FXU_power6")
diff --git a/gcc/config/rs6000/power7.md b/gcc/config/rs6000/power7.md
index 00aa26b..b2a0caf 100644
--- a/gcc/config/rs6000/power7.md
+++ b/gcc/config/rs6000/power7.md
@@ -175,7 +175,7 @@ (define_insn_reservation "power7-sync" 11
; FX Unit
(define_insn_reservation "power7-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,exts,isel,popcnt")
- (and (eq_attr "type" "add,shift")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
@@ -196,8 +196,8 @@ (define_insn_reservation "power7-three" 3
"DU_power7+DU_power7+DU_power7,FXU_power7,FXU_power7,FXU_power7")
(define_insn_reservation "power7-cmp" 1
- (and (ior (eq_attr "type" "cmp,fast_compare")
- (and (eq_attr "type" "add")
+ (and (ior (eq_attr "type" "cmp")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md
index b2eeac4..c7c0aa9 100644
--- a/gcc/config/rs6000/power8.md
+++ b/gcc/config/rs6000/power8.md
@@ -169,7 +169,7 @@ (define_insn_reservation "power8-sync" 1
; FX Unit
(define_insn_reservation "power8-1cyc" 1
(and (ior (eq_attr "type" "integer,insert,trap,exts,isel")
- (and (eq_attr "type" "add,shift")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
@@ -205,11 +205,10 @@ (define_insn_reservation "power8-cmp" 2
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
-; fast_compare : add./and./nor./etc
+; add/logical with dot : add./and./nor./etc
(define_insn_reservation "power8-fast-compare" 2
- (and (ior (eq_attr "type" "fast_compare")
- (and (eq_attr "type" "add")
- (eq_attr "dot" "yes")))
+ (and (eq_attr "type" "add,logical")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index c4f4df2..b3f404b 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -26241,8 +26241,8 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
}
case TYPE_INTEGER:
case TYPE_ADD:
+ case TYPE_LOGICAL:
case TYPE_COMPARE:
- case TYPE_FAST_COMPARE:
case TYPE_EXTS:
case TYPE_INSERT:
{
@@ -26305,8 +26305,8 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
}
case TYPE_INTEGER:
case TYPE_ADD:
+ case TYPE_LOGICAL:
case TYPE_COMPARE:
- case TYPE_FAST_COMPARE:
case TYPE_EXTS:
case TYPE_INSERT:
{
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3f6cefd..1bf0c30 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -159,13 +159,13 @@ (define_c_enum "unspecv"
;; computations.
(define_attr "type"
"integer,two,three,
- add,shift,insert,
+ add,logical,shift,insert,
mul,halfmul,div,
exts,cntlz,popcnt,isel,
load,store,fpload,fpstore,vecload,vecstore,
cmp,
branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
- compare,fast_compare,
+ compare,
cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
brinc,
@@ -179,7 +179,7 @@ (define_attr "type"
(define_attr "size" "8,16,32,64" (const_string "32"))
;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
-;; This is used for mul.
+;; This is used for add, logical, shift, mul.
(define_attr "dot" "no,yes" (const_string "no"))
;; Does this instruction sign-extend its result?
@@ -877,7 +877,8 @@ (define_insn ""
"@
andi. %2,%1,0xff
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -903,7 +904,8 @@ (define_insn ""
"@
andi. %0,%1,0xff
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -997,7 +999,8 @@ (define_insn ""
"@
andi. %2,%1,0xff
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -1023,7 +1026,8 @@ (define_insn ""
"@
andi. %0,%1,0xff
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -1123,7 +1127,8 @@ (define_insn ""
"@
andi. %2,%1,0xffff
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -1149,7 +1154,8 @@ (define_insn ""
"@
andi. %0,%1,0xffff
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -1952,7 +1958,8 @@ (define_insn ""
"@
nor. %2,%1,%1
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -1978,7 +1985,8 @@ (define_insn ""
"@
nor. %0,%1,%1
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -2907,7 +2915,8 @@ (define_insn "andsi3_mc"
rlwinm %0,%1,0,%m2,%M2
andi. %0,%1,%b2
andis. %0,%1,%u2"
- [(set_attr "type" "*,*,fast_compare,fast_compare")])
+ [(set_attr "type" "*,*,logical,logical")
+ (set_attr "dot" "no,no,yes,yes")])
(define_insn "andsi3_nomc"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -2950,7 +2959,7 @@ (define_insn "*andsi3_internal2_mc"
#
#
#"
- [(set_attr "type" "fast_compare,fast_compare,fast_compare,shift,\
+ [(set_attr "type" "logical,logical,logical,shift,\
compare,compare,compare,compare")
(set_attr "dot" "yes")
(set_attr "length" "4,4,4,4,8,8,8,8")])
@@ -2972,7 +2981,7 @@ (define_insn "*andsi3_internal3_mc"
#
#
#"
- [(set_attr "type" "compare,fast_compare,fast_compare,shift,compare,\
+ [(set_attr "type" "compare,logical,logical,shift,compare,\
compare,compare,compare")
(set_attr "dot" "yes")
(set_attr "length" "8,4,4,4,8,8,8,8")])
@@ -3033,7 +3042,7 @@ (define_insn "*andsi3_internal4"
#
#
#"
- [(set_attr "type" "fast_compare,fast_compare,fast_compare,shift,\
+ [(set_attr "type" "logical,logical,logical,shift,\
compare,compare,compare,compare")
(set_attr "dot" "yes")
(set_attr "length" "4,4,4,4,8,8,8,8")])
@@ -3057,7 +3066,7 @@ (define_insn "*andsi3_internal5_mc"
#
#
#"
- [(set_attr "type" "compare,fast_compare,fast_compare,shift,compare,\
+ [(set_attr "type" "compare,logical,logical,shift,compare,\
compare,compare,compare")
(set_attr "dot" "yes")
(set_attr "length" "8,4,4,4,8,8,8,8")])
@@ -3190,7 +3199,8 @@ (define_insn "*boolsi3_internal2"
"@
%q4. %3,%1,%2
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -3219,7 +3229,8 @@ (define_insn "*boolsi3_internal3"
"@
%q4. %0,%1,%2
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -3344,7 +3355,8 @@ (define_insn "*boolccsi3_internal2"
"@
%q4. %3,%1,%2
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -3373,7 +3385,8 @@ (define_insn "*boolccsi3_internal3"
"@
%q4. %0,%1,%2
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -4550,7 +4563,7 @@ (define_insn ""
#
#
#"
- [(set_attr "type" "fast_compare,shift,shift,shift,shift,shift")
+ [(set_attr "type" "logical,shift,shift,shift,shift,shift")
(set_attr "var_shift" "no,yes,no,no,yes,no")
(set_attr "dot" "yes")
(set_attr "length" "4,4,4,8,8,8")])
@@ -4584,7 +4597,7 @@ (define_insn ""
#
#
#"
- [(set_attr "type" "fast_compare,shift,shift,shift,shift,shift")
+ [(set_attr "type" "logical,shift,shift,shift,shift,shift")
(set_attr "var_shift" "no,yes,no,no,yes,no")
(set_attr "dot" "yes")
(set_attr "length" "4,4,4,8,8,8")])
@@ -8071,7 +8084,8 @@ (define_insn "anddi3_mc"
andi. %0,%1,%b2
andis. %0,%1,%u2
#"
- [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
+ [(set_attr "type" "*,*,*,logical,logical,*")
+ (set_attr "dot" "no,no,no,yes,yes,no")
(set_attr "length" "4,4,4,4,4,8")])
(define_insn "anddi3_nomc"
@@ -8129,8 +8143,8 @@ (define_insn "*anddi3_internal2_mc"
#
#
#"
- [(set_attr "type" "fast_compare,compare,shift,fast_compare,\
- fast_compare,compare,compare,compare,compare,compare,\
+ [(set_attr "type" "logical,compare,shift,logical,\
+ logical,compare,compare,compare,compare,compare,\
compare,compare")
(set_attr "dot" "yes")
(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
@@ -8183,8 +8197,8 @@ (define_insn "*anddi3_internal3_mc"
#
#
#"
- [(set_attr "type" "fast_compare,compare,shift,fast_compare,\
- fast_compare,compare,compare,compare,compare,compare,\
+ [(set_attr "type" "logical,compare,shift,logical,\
+ logical,compare,compare,compare,compare,compare,\
compare,compare")
(set_attr "dot" "yes")
(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
@@ -8316,7 +8330,8 @@ (define_insn "*booldi3_internal2"
"@
%q4. %3,%1,%2
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -8345,7 +8360,8 @@ (define_insn "*booldi3_internal3"
"@
%q4. %0,%1,%2
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -8405,7 +8421,8 @@ (define_insn "*boolcdi3_internal2"
"@
%q4. %3,%2,%1
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -8434,7 +8451,8 @@ (define_insn "*boolcdi3_internal3"
"@
%q4. %0,%2,%1
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -8471,7 +8489,8 @@ (define_insn "*boolccdi3_internal2"
"@
%q4. %3,%1,%2
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -8500,7 +8519,8 @@ (define_insn "*boolccdi3_internal3"
"@
%q4. %0,%1,%2
#"
- [(set_attr "type" "fast_compare,compare")
+ [(set_attr "type" "logical,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -9039,7 +9059,8 @@ (define_insn "*mov<mode>_internal2"
cmp<wd>i %2,%0,0
mr. %0,%1
#"
- [(set_attr "type" "cmp,fast_compare,cmp")
+ [(set_attr "type" "cmp,logical,cmp")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8")])
(define_split
diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md
index 2c32415..c891ac4 100644
--- a/gcc/config/rs6000/rs64.md
+++ b/gcc/config/rs6000/rs64.md
@@ -47,7 +47,7 @@ (define_insn_reservation "rs64a-llsc" 2
(define_insn_reservation "rs64a-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "add,shift")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "rs64a"))
"iu_rs64")
@@ -99,8 +99,8 @@ (define_insn_reservation "rs64a-ldiv" 66
"mciu_rs64*66")
(define_insn_reservation "rs64a-compare" 3
- (and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "add,shift")
+ (and (ior (eq_attr "type" "cmp,compare")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "rs64a"))
"iu_rs64,nothing,bpu_rs64")
diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md
index cb284ff..4326cb9 100644
--- a/gcc/config/rs6000/titan.md
+++ b/gcc/config/rs6000/titan.md
@@ -34,8 +34,8 @@ (define_cpu_unit "titan_fxu_sh,titan_fxu_wb" "titan_fxu")
;; instructions. It provides its own, dedicated result-bus, so we
;; don't need the titan_fxu_wb reservation to complete.
(define_insn_reservation "titan_fxu_adder" 1
- (and (ior (eq_attr "type" "cmp,fast_compare,trap")
- (and (eq_attr "type" "add")
+ (and (ior (eq_attr "type" "cmp,trap")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh")
@@ -75,7 +75,7 @@ (define_insn_reservation "titan_fxu_div" 34
(define_insn_reservation "titan_fxu_alu" 1
(and (ior (eq_attr "type" "integer,exts")
- (and (eq_attr "type" "add")
+ (and (eq_attr "type" "add,logical")
(eq_attr "dot" "no")))
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing,titan_fxu_wb")
--
1.8.1.4
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 9/9] rs6000: Make all rlw*nm and rld*c* type shift
2014-05-23 6:13 [PATCH 1/9] rs6000: Clean up the "type" attribute Segher Boessenkool
` (5 preceding siblings ...)
2014-05-23 6:56 ` [PATCH 5/9] rs6000: Make all divide " Segher Boessenkool
@ 2014-05-23 6:56 ` Segher Boessenkool
2014-05-23 13:47 ` David Edelsohn
2014-05-23 6:57 ` [PATCH 6/9] rs6000: Make all shift instructions one type Segher Boessenkool
2014-05-23 13:36 ` [PATCH 1/9] rs6000: Clean up the "type" attribute David Edelsohn
8 siblings, 1 reply; 20+ messages in thread
From: Segher Boessenkool @ 2014-05-23 6:56 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
They are often labeled just "integer" currently. Fix that.
Also handle shift properly in those scheduling descriptions that
neglected it.
2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
gcc/
* config/rs6000/440.md (ppc440-integer): Include shift without
dot.
(ppc440-compare): Include shift with dot.
* config/rs6000/e300c2c3.md (ppce300c3_iu): Include shift without
dot.
* config/rs6000/e5500.md (e5500_sfx2): Include constant shift
without dot.
* config/rs6000/e6500.md (e6500_sfx): Exclude constant shift
without dot.
(e6500_sfx2): Include it.
* config/rs6000/rs6000.md ( *zero_extend<mode>di2_internal1,
*zero_extend<mode>di2_internal2, *zero_extend<mode>di2_internal3,
*zero_extendsidi2_lfiwzx, andsi3_mc, andsi3_nomc,
andsi3_internal0_nomc, extzvsi_internal, extzvdi_internal,
*extzvdi_internal1, *extzvdi_internal2, rotlsi3, *rotlsi3_64,
*rotlsi3_internal4, *rotlsi3_internal7le, *rotlsi3_internal7be,
*rotlsi3_internal10le, *rotlsi3_internal10be, rlwinm,
*lshiftrt_internal1le, *lshiftrt_internal1be,
*lshiftrt_internal4le, *lshiftrt_internal4be, rotldi3,
*rotldi3_internal4, *rotldi3_internal7le, *rotldi3_internal7be,
*rotldi3_internal10le, *rotldi3_internal10be,
*rotldi3_internal13le, *rotldi3_internal13be, *ashldi3_internal4,
ashldi3_internal5, *ashldi3_internal6, *ashldi3_internal7,
ashldi3_internal8, *ashldi3_internal9, anddi3_mc, anddi3_nomc,
*anddi3_internal2_mc, *anddi3_internal3_mc, and 4 anonymous
define_insns): Use type "shift" in the appropriate alternatives.
---
gcc/config/rs6000/440.md | 6 +--
gcc/config/rs6000/e300c2c3.md | 2 +-
gcc/config/rs6000/e5500.md | 5 +-
gcc/config/rs6000/e6500.md | 6 ++-
gcc/config/rs6000/rs6000.md | 113 +++++++++++++++++++++++++-----------------
5 files changed, 81 insertions(+), 51 deletions(-)
diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md
index bc8da3e..f956bd6 100644
--- a/gcc/config/rs6000/440.md
+++ b/gcc/config/rs6000/440.md
@@ -53,8 +53,8 @@ (define_insn_reservation "ppc440-fpstore" 3
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1
- (and (ior (eq_attr "type" "integer,insert,shift,trap,cntlz,exts,isel")
- (and (eq_attr "type" "add,logical")
+ (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
@@ -96,7 +96,7 @@ (define_insn_reservation "ppc440-branch" 1
(define_insn_reservation "ppc440-compare" 2
(and (ior (eq_attr "type" "cmp,compare,cr_logical,delayed_cr,mfcr")
- (and (eq_attr "type" "add,logical")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md
index 6ac585b..f80ef30 100644
--- a/gcc/config/rs6000/e300c2c3.md
+++ b/gcc/config/rs6000/e300c2c3.md
@@ -93,7 +93,7 @@ (define_insn_reservation "ppce300c3_cmp" 1
;; Other one cycle IU insns
(define_insn_reservation "ppce300c3_iu" 1
(and (ior (eq_attr "type" "integer,insert,isel")
- (and (eq_attr "type" "add,logical")
+ (and (eq_attr "type" "add,logical,shift")
(eq_attr "dot" "no")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
diff --git a/gcc/config/rs6000/e5500.md b/gcc/config/rs6000/e5500.md
index 49a5c39..8d784e0 100644
--- a/gcc/config/rs6000/e5500.md
+++ b/gcc/config/rs6000/e5500.md
@@ -67,7 +67,10 @@ (define_insn_reservation "e5500_sfx" 1
(define_insn_reservation "e5500_sfx2" 2
(and (ior (eq_attr "type" "cmp,compare,trap")
(and (eq_attr "type" "add,logical")
- (eq_attr "dot" "yes")))
+ (eq_attr "dot" "yes"))
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")
+ (eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md
index deec34b..a013a94 100644
--- a/gcc/config/rs6000/e6500.md
+++ b/gcc/config/rs6000/e6500.md
@@ -63,6 +63,7 @@ (define_insn_reservation "e6500_sfx" 1
(and (eq_attr "type" "add,logical")
(eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
@@ -70,7 +71,10 @@ (define_insn_reservation "e6500_sfx" 1
(define_insn_reservation "e6500_sfx2" 2
(and (ior (eq_attr "type" "cmp,compare,trap")
(and (eq_attr "type" "add,logical")
- (eq_attr "dot" "yes")))
+ (eq_attr "dot" "yes"))
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")
+ (eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1bf0c30..cafb396 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -565,7 +565,7 @@ (define_insn "*zero_extend<mode>di2_internal1"
"@
l<wd>z%U1%X1 %0,%1
rldicl %0,%1,0,<dbits>"
- [(set_attr "type" "load,*")])
+ [(set_attr "type" "load,shift")])
(define_insn "*zero_extend<mode>di2_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -576,7 +576,8 @@ (define_insn "*zero_extend<mode>di2_internal2"
"@
rldicl. %2,%1,0,<dbits>
#"
- [(set_attr "type" "compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -602,7 +603,8 @@ (define_insn "*zero_extend<mode>di2_internal3"
"@
rldicl. %0,%1,0,<dbits>
#"
- [(set_attr "type" "compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -629,7 +631,7 @@ (define_insn "*zero_extendsidi2_lfiwzx"
mtvsrwz %x0,%1
lfiwzx %0,%y1
lxsiwzx %x0,%y1"
- [(set_attr "type" "load,*,mffgpr,fpload,fpload")])
+ [(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
(define_insn "extendqidi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
@@ -866,7 +868,7 @@ (define_insn ""
"@
lbz%U1%X1 %0,%1
rlwinm %0,%1,0,0xff"
- [(set_attr "type" "load,*")])
+ [(set_attr "type" "load,shift")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -988,7 +990,7 @@ (define_insn ""
"@
lbz%U1%X1 %0,%1
rlwinm %0,%1,0,0xff"
- [(set_attr "type" "load,*")])
+ [(set_attr "type" "load,shift")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -1116,7 +1118,7 @@ (define_insn ""
"@
lhz%U1%X1 %0,%1
rlwinm %0,%1,0,0xffff"
- [(set_attr "type" "load,*")])
+ [(set_attr "type" "load,shift")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -2915,7 +2917,7 @@ (define_insn "andsi3_mc"
rlwinm %0,%1,0,%m2,%M2
andi. %0,%1,%b2
andis. %0,%1,%u2"
- [(set_attr "type" "*,*,logical,logical")
+ [(set_attr "type" "*,shift,logical,logical")
(set_attr "dot" "no,no,yes,yes")])
(define_insn "andsi3_nomc"
@@ -2926,7 +2928,8 @@ (define_insn "andsi3_nomc"
"!rs6000_gen_cell_microcode"
"@
and %0,%1,%2
- rlwinm %0,%1,0,%m2,%M2")
+ rlwinm %0,%1,0,%m2,%M2"
+ [(set_attr "type" "logical,shift")])
(define_insn "andsi3_internal0_nomc"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -2935,7 +2938,8 @@ (define_insn "andsi3_internal0_nomc"
"!rs6000_gen_cell_microcode"
"@
and %0,%1,%2
- rlwinm %0,%1,0,%m2,%M2")
+ rlwinm %0,%1,0,%m2,%M2"
+ [(set_attr "type" "logical,shift")])
;; Note to set cr's other than cr0 we do the and immediate and then
@@ -3665,7 +3669,8 @@ (define_insn "extzvsi_internal"
else
operands[3] = GEN_INT (start + size);
return \"rlwinm %0,%1,%3,%s2,31\";
-}")
+}"
+ [(set_attr "type" "shift")])
(define_insn "*extzvsi_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -3795,7 +3800,8 @@ (define_insn "extzvdi_internal"
operands[3] = GEN_INT (start + size);
operands[2] = GEN_INT (64 - size);
return \"rldicl %0,%1,%3,%2\";
-}")
+}"
+ [(set_attr "type" "shift")])
(define_insn "*extzvdi_internal1"
[(set (match_operand:CC 0 "gpc_reg_operand" "=x")
@@ -3817,7 +3823,8 @@ (define_insn "*extzvdi_internal1"
operands[2] = GEN_INT (64 - size);
return \"rldicl. %4,%1,%3,%2\";
}"
- [(set_attr "type" "compare")])
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")])
(define_insn "*extzvdi_internal2"
[(set (match_operand:CC 4 "gpc_reg_operand" "=x")
@@ -3840,7 +3847,8 @@ (define_insn "*extzvdi_internal2"
operands[2] = GEN_INT (64 - size);
return \"rldicl. %0,%1,%3,%2\";
}"
- [(set_attr "type" "compare")])
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")])
(define_insn "rotlsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -3850,7 +3858,7 @@ (define_insn "rotlsi3"
"@
rlwnm %0,%1,%2,0xffffffff
rlwinm %0,%1,%h2,0xffffffff"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_64"
@@ -3862,7 +3870,7 @@ (define_insn "*rotlsi3_64"
"@
rlwnm %0,%1,%2,0xffffffff
rlwinm %0,%1,%h2,0xffffffff"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_internal2"
@@ -3938,7 +3946,7 @@ (define_insn "*rotlsi3_internal4"
"@
rlwnm %0,%1,%2,%m3,%M3
rlwinm %0,%1,%h2,%m3,%M3"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_internal5"
@@ -4026,7 +4034,8 @@ (define_insn "*rotlsi3_internal7le"
[(set (attr "cell_micro")
(if_then_else (match_operand:SI 2 "const_int_operand" "")
(const_string "not")
- (const_string "always")))])
+ (const_string "always")))
+ (set_attr "type" "shift")])
(define_insn "*rotlsi3_internal7be"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -4039,7 +4048,8 @@ (define_insn "*rotlsi3_internal7be"
[(set (attr "cell_micro")
(if_then_else (match_operand:SI 2 "const_int_operand" "")
(const_string "not")
- (const_string "always")))])
+ (const_string "always")))
+ (set_attr "type" "shift")])
(define_insn "*rotlsi3_internal8le"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -4199,7 +4209,7 @@ (define_insn "*rotlsi3_internal10le"
"@
rlwnm %0,%1,%2,0xffff
rlwinm %0,%1,%h2,0xffff"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_internal10be"
@@ -4212,7 +4222,7 @@ (define_insn "*rotlsi3_internal10be"
"@
rlwnm %0,%1,%2,0xffff
rlwinm %0,%1,%h2,0xffff"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_internal11le"
@@ -4456,7 +4466,8 @@ (define_insn "rlwinm"
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "n")))]
"includes_lshift_p (operands[2], operands[3])"
- "rlwinm %0,%1,%h2,%m3,%M3")
+ "rlwinm %0,%1,%h2,%m3,%M3"
+ [(set_attr "type" "shift")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -4623,7 +4634,8 @@ (define_insn ""
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "n")))]
"includes_rshift_p (operands[2], operands[3])"
- "rlwinm %0,%1,%s2,%m3,%M3")
+ "rlwinm %0,%1,%s2,%m3,%M3"
+ [(set_attr "type" "shift")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -4699,7 +4711,8 @@ (define_insn "*lshiftrt_internal1le"
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0)))]
"!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
- "rlwinm %0,%1,%s2,0xff")
+ "rlwinm %0,%1,%s2,0xff"
+ [(set_attr "type" "shift")])
(define_insn "*lshiftrt_internal1be"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -4708,7 +4721,8 @@ (define_insn "*lshiftrt_internal1be"
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 3)))]
"BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
- "rlwinm %0,%1,%s2,0xff")
+ "rlwinm %0,%1,%s2,0xff"
+ [(set_attr "type" "shift")])
(define_insn "*lshiftrt_internal2le"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -4861,7 +4875,8 @@ (define_insn "*lshiftrt_internal4le"
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0)))]
"!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
- "rlwinm %0,%1,%s2,0xffff")
+ "rlwinm %0,%1,%s2,0xffff"
+ [(set_attr "type" "shift")])
(define_insn "*lshiftrt_internal4be"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -4870,7 +4885,8 @@ (define_insn "*lshiftrt_internal4be"
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 2)))]
"BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
- "rlwinm %0,%1,%s2,0xffff")
+ "rlwinm %0,%1,%s2,0xffff"
+ [(set_attr "type" "shift")])
(define_insn "*lshiftrt_internal5le"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -6969,7 +6985,7 @@ (define_insn "rotldi3"
"@
rldcl %0,%1,%2,0
rldicl %0,%1,%H2,0"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal2"
@@ -7045,7 +7061,7 @@ (define_insn "*rotldi3_internal4"
"@
rldc%B3 %0,%1,%2,%S3
rldic%B3 %0,%1,%H2,%S3"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal5"
@@ -7132,7 +7148,7 @@ (define_insn "*rotldi3_internal7le"
"@
rldcl %0,%1,%2,56
rldicl %0,%1,%H2,56"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal7be"
@@ -7145,7 +7161,7 @@ (define_insn "*rotldi3_internal7be"
"@
rldcl %0,%1,%2,56
rldicl %0,%1,%H2,56"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal8le"
@@ -7306,7 +7322,7 @@ (define_insn "*rotldi3_internal10le"
"@
rldcl %0,%1,%2,48
rldicl %0,%1,%H2,48"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal10be"
@@ -7319,7 +7335,7 @@ (define_insn "*rotldi3_internal10be"
"@
rldcl %0,%1,%2,48
rldicl %0,%1,%H2,48"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal11le"
@@ -7480,7 +7496,7 @@ (define_insn "*rotldi3_internal13le"
"@
rldcl %0,%1,%2,32
rldicl %0,%1,%H2,32"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal13be"
@@ -7493,7 +7509,7 @@ (define_insn "*rotldi3_internal13be"
"@
rldcl %0,%1,%2,32
rldicl %0,%1,%H2,32"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal14le"
@@ -7732,7 +7748,8 @@ (define_insn "*ashldi3_internal4"
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:DI 3 "const_int_operand" "n")))]
"TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
- "rldic %0,%1,%H2,%W3")
+ "rldic %0,%1,%H2,%W3"
+ [(set_attr "type" "shift")])
(define_insn "ashldi3_internal5"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -7746,7 +7763,8 @@ (define_insn "ashldi3_internal5"
"@
rldic. %4,%1,%H2,%W3
#"
- [(set_attr "type" "compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -7780,7 +7798,8 @@ (define_insn "*ashldi3_internal6"
"@
rldic. %0,%1,%H2,%W3
#"
- [(set_attr "type" "compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -7808,7 +7827,8 @@ (define_insn "*ashldi3_internal7"
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:DI 3 "mask64_operand" "n")))]
"TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
- "rldicr %0,%1,%H2,%S3")
+ "rldicr %0,%1,%H2,%S3"
+ [(set_attr "type" "shift")])
(define_insn "ashldi3_internal8"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -7822,7 +7842,8 @@ (define_insn "ashldi3_internal8"
"@
rldicr. %4,%1,%H2,%S3
#"
- [(set_attr "type" "compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -7856,7 +7877,8 @@ (define_insn "*ashldi3_internal9"
"@
rldicr. %0,%1,%H2,%S3
#"
- [(set_attr "type" "compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -8084,7 +8106,7 @@ (define_insn "anddi3_mc"
andi. %0,%1,%b2
andis. %0,%1,%u2
#"
- [(set_attr "type" "*,*,*,logical,logical,*")
+ [(set_attr "type" "*,shift,shift,logical,logical,*")
(set_attr "dot" "no,no,no,yes,yes,no")
(set_attr "length" "4,4,4,4,4,8")])
@@ -8099,7 +8121,8 @@ (define_insn "anddi3_nomc"
rldic%B2 %0,%1,0,%S2
rlwinm %0,%1,0,%m2,%M2
#"
- [(set_attr "length" "4,4,4,8")])
+ [(set_attr "type" "*,shift,shift,*")
+ (set_attr "length" "4,4,4,8")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -8143,7 +8166,7 @@ (define_insn "*anddi3_internal2_mc"
#
#
#"
- [(set_attr "type" "logical,compare,shift,logical,\
+ [(set_attr "type" "logical,shift,shift,logical,\
logical,compare,compare,compare,compare,compare,\
compare,compare")
(set_attr "dot" "yes")
@@ -8197,7 +8220,7 @@ (define_insn "*anddi3_internal3_mc"
#
#
#"
- [(set_attr "type" "logical,compare,shift,logical,\
+ [(set_attr "type" "logical,shift,shift,logical,\
logical,compare,compare,compare,compare,compare,\
compare,compare")
(set_attr "dot" "yes")
--
1.8.1.4
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 6/9] rs6000: Make all shift instructions one type
2014-05-23 6:13 [PATCH 1/9] rs6000: Clean up the "type" attribute Segher Boessenkool
` (6 preceding siblings ...)
2014-05-23 6:56 ` [PATCH 9/9] rs6000: Make all rlw*nm and rld*c* type shift Segher Boessenkool
@ 2014-05-23 6:57 ` Segher Boessenkool
2014-05-23 13:43 ` David Edelsohn
2014-05-23 13:36 ` [PATCH 1/9] rs6000: Clean up the "type" attribute David Edelsohn
8 siblings, 1 reply; 20+ messages in thread
From: Segher Boessenkool @ 2014-05-23 6:57 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
This uses the attributes "var_shift" and "dot" to specify the differences:
var_shift_rotate -> shift var_shift=yes
delayed_compare -> shift var_shift=no dot=yes
var_delayed_compare -> shift var_shift=yes dot=yes
2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
gcc/
* config/rs6000/rs6000.md (type): Delete "var_shift_rotate",
"delayed_compare", "var_delayed_compare".
(var_shift): New attribute.
(cell_micro): Adjust.
(*andsi3_internal2_mc, *andsi3_internal3_mc, *andsi3_internal4,
*andsi3_internal5_mc, *extzvsi_internal1, *extzvsi_internal2,
rotlsi3, *rotlsi3_64, *rotlsi3_internal2, *rotlsi3_internal3,
*rotlsi3_internal4, *rotlsi3_internal5, *rotlsi3_internal6,
*rotlsi3_internal8le, *rotlsi3_internal8be, *rotlsi3_internal9le,
*rotlsi3_internal9be, *rotlsi3_internal10le, *rotlsi3_internal10be,
*rotlsi3_internal11le, *rotlsi3_internal11be, *rotlsi3_internal12le,
*rotlsi3_internal12be, ashlsi3, *ashlsi3_64, lshrsi3, *lshrsi3_64,
*lshiftrt_internal2le, *lshiftrt_internal2be, *lshiftrt_internal3le,
*lshiftrt_internal3be, *lshiftrt_internal5le, *lshiftrt_internal5be,
*lshiftrt_internal5le, *lshiftrt_internal5be, ashrsi3, *ashrsi3_64,
rotldi3, *rotldi3_internal2, *rotldi3_internal3, *rotldi3_internal4,
*rotldi3_internal5, *rotldi3_internal6, *rotldi3_internal7le,
*rotldi3_internal7be, *rotldi3_internal8le, *rotldi3_internal8be,
*rotldi3_internal9le, *rotldi3_internal9be, *rotldi3_internal10le,
*rotldi3_internal10be, *rotldi3_internal11le, *rotldi3_internal11be,
*rotldi3_internal12le, *rotldi3_internal12be, *rotldi3_internal13le,
*rotldi3_internal13be, *rotldi3_internal14le, *rotldi3_internal14be,
*rotldi3_internal15le, *rotldi3_internal15be, *ashldi3_internal1,
*ashldi3_internal2, *ashldi3_internal3, *lshrdi3_internal1,
*lshrdi3_internal2, *lshrdi3_internal3, *ashrdi3_internal1,
*ashrdi3_internal2, *ashrdi3_internal3, *anddi3_internal2_mc,
*anddi3_internal3_mc, as well as 11 anonymous define_insns): Adjust.
* config/rs6000/rs6000.c (rs6000_adjust_cost, is_cracked_insn,
insn_must_be_first_in_group, insn_must_be_last_in_group): Adjust.
* config/rs6000/40x.md (ppc403-integer, ppc403-compare): Adjust.
* config/rs6000/440.md (ppc440-integer): Adjust.
* config/rs6000/476.md (ppc476-simple-integer, ppc476-compare):
Adjust.
* config/rs6000/601.md (ppc601-integer, ppc601-compare): Adjust.
* config/rs6000/603.md (ppc603-integer, ppc603-compare): Adjust.
* config/rs6000/6xx.md (ppc604-integer, ppc604-compare): Adjust.
* config/rs6000/7450.md (ppc7450-integer, ppc7450-compare):
Adjust.
* config/rs6000/7xx.md (ppc750-integer, ppc750-compare): Adjust.
* config/rs6000/8540.md (ppc8540_su): Adjust.
* config/rs6000/cell.md (cell-integer, cell-fast-cmp,
cell-cmp-microcoded): Adjust.
* config/rs6000/e300c2c3.md (ppce300c3_cmp): Adjust.
* config/rs6000/e500mc.md (e500mc_su): Adjust.
* config/rs6000/e500mc64.md (e500mc64_su, e500mc64_su2,
e500mc64_delayed): Adjust.
* config/rs6000/e5500.md (e5500_sfx, e5500_delayed): Adjust.
* config/rs6000/e6500.md (e6500_sfx, e6500_delayed): Adjust.
* config/rs6000/mpc.md (mpccore-integer, mpccore-compare): Adjust.
* config/rs6000/power4.md (power4-integer, power4-compare):
Adjust.
* config/rs6000/power5.md (power5-integer, power5-compare):
Adjust.
* config/rs6000/power6.md (power6-shift, power6-var-rotate,
power6-delayed-compare, power6-var-delayed-compare): Adjust.
* config/rs6000/power7.md (power7-integer, power7-compare):
Adjust.
* config/rs6000/power8.md (power8-1cyc, power8-compare): Adjust.
Adjust comment.
* config/rs6000/rs64.md (rs64a-integer, rs64a-compare): Adjust.
* config/rs6000/titan.md (titan_fxu_shift_and_rotate): Adjust.
---
gcc/config/rs6000/40x.md | 10 +-
gcc/config/rs6000/440.md | 3 +-
gcc/config/rs6000/476.md | 10 +-
gcc/config/rs6000/601.md | 10 +-
gcc/config/rs6000/603.md | 10 +-
gcc/config/rs6000/6xx.md | 10 +-
gcc/config/rs6000/7450.md | 10 +-
gcc/config/rs6000/7xx.md | 10 +-
gcc/config/rs6000/8540.md | 5 +-
gcc/config/rs6000/cell.md | 23 ++--
gcc/config/rs6000/e300c2c3.md | 4 +-
gcc/config/rs6000/e500mc.md | 5 +-
gcc/config/rs6000/e500mc64.md | 14 +-
gcc/config/rs6000/e5500.md | 8 +-
gcc/config/rs6000/e6500.md | 8 +-
gcc/config/rs6000/mpc.md | 10 +-
gcc/config/rs6000/power4.md | 9 +-
gcc/config/rs6000/power5.md | 9 +-
gcc/config/rs6000/power6.md | 14 +-
gcc/config/rs6000/power7.md | 9 +-
gcc/config/rs6000/power8.md | 12 +-
gcc/config/rs6000/rs6000.c | 57 +++++---
gcc/config/rs6000/rs6000.md | 308 ++++++++++++++++++++++++++++++------------
gcc/config/rs6000/rs64.md | 10 +-
gcc/config/rs6000/titan.md | 2 +-
25 files changed, 388 insertions(+), 192 deletions(-)
diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md
index 8ddccba..30ac01d 100644
--- a/gcc/config/rs6000/40x.md
+++ b/gcc/config/rs6000/40x.md
@@ -36,8 +36,9 @@ (define_insn_reservation "ppc403-store" 2
"iu_40x")
(define_insn_reservation "ppc403-integer" 1
- (and (eq_attr "type" "integer,insert,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
@@ -52,8 +53,9 @@ (define_insn_reservation "ppc403-three" 1
"iu_40x,iu_40x,iu_40x")
(define_insn_reservation "ppc403-compare" 3
- (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,nothing,bpu_40x")
diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md
index e6c28a7..3a36ffb 100644
--- a/gcc/config/rs6000/440.md
+++ b/gcc/config/rs6000/440.md
@@ -53,8 +53,7 @@ (define_insn_reservation "ppc440-fpstore" 3
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1
- (and (eq_attr "type" "integer,insert,shift,\
- trap,var_shift_rotate,cntlz,exts,isel")
+ (and (eq_attr "type" "integer,insert,shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md
index 5acd668..41cd247 100644
--- a/gcc/config/rs6000/476.md
+++ b/gcc/config/rs6000/476.md
@@ -63,7 +63,9 @@ (define_insn_reservation "ppc476-fpstore" 4
ppc476_lj_pipe")
(define_insn_reservation "ppc476-simple-integer" 1
- (and (eq_attr "type" "integer,insert,var_shift_rotate,exts,shift")
+ (and (ior (eq_attr "type" "integer,insert,exts")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe|ppc476_lj_pipe")
@@ -75,8 +77,10 @@ (define_insn_reservation "ppc476-complex-integer" 1
ppc476_i_pipe")
(define_insn_reservation "ppc476-compare" 4
- (and (eq_attr "type" "compare,delayed_compare,fast_compare,mfcr,mfcrf,\
- mtcr,mfjmpr,mtjmpr,var_delayed_compare")
+ (and (ior (eq_attr "type" "compare,fast_compare,mfcr,mfcrf,\
+ mtcr,mfjmpr,mtjmpr")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe")
diff --git a/gcc/config/rs6000/601.md b/gcc/config/rs6000/601.md
index 85892c8..f6eca7d 100644
--- a/gcc/config/rs6000/601.md
+++ b/gcc/config/rs6000/601.md
@@ -45,8 +45,9 @@ (define_insn_reservation "ppc601-fpstore" 3
"iu_ppc601+fpu_ppc601")
(define_insn_reservation "ppc601-integer" 1
- (and (eq_attr "type" "integer,insert,shift,\
- trap,var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc601"))
"iu_ppc601")
@@ -73,8 +74,9 @@ (define_insn_reservation "ppc601-idiv" 36
; compare executes on integer unit, but feeds insns which
; execute on the branch unit.
(define_insn_reservation "ppc601-compare" 3
- (and (eq_attr "type" "cmp,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc601"))
"iu_ppc601,nothing,bpu_ppc601")
diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md
index 5f38741..f64f428 100644
--- a/gcc/config/rs6000/603.md
+++ b/gcc/config/rs6000/603.md
@@ -58,8 +58,9 @@ (define_insn_reservation "ppc603-storec" 8
"lsu_603")
(define_insn_reservation "ppc603-integer" 1
- (and (eq_attr "type" "integer,insert,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc603"))
"iu_603")
@@ -92,8 +93,9 @@ (define_insn_reservation "ppc603-idiv" 37
"iu_603*37")
(define_insn_reservation "ppc603-compare" 3
- (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc603"))
"iu_603,nothing,bpu_603")
diff --git a/gcc/config/rs6000/6xx.md b/gcc/config/rs6000/6xx.md
index 3ff4caf..6d4ccb7 100644
--- a/gcc/config/rs6000/6xx.md
+++ b/gcc/config/rs6000/6xx.md
@@ -73,8 +73,9 @@ (define_insn_reservation "ppc630-llsc" 4
"lsu_6xx")
(define_insn_reservation "ppc604-integer" 1
- (and (eq_attr "type" "integer,insert,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
@@ -146,8 +147,9 @@ (define_insn_reservation "ppc620-ldiv" 37
"mciu_6xx*36")
(define_insn_reservation "ppc604-compare" 3
- (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"(iu1_6xx|iu2_6xx)")
diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md
index 3333fd9..39815e9 100644
--- a/gcc/config/rs6000/7450.md
+++ b/gcc/config/rs6000/7450.md
@@ -73,8 +73,9 @@ (define_insn_reservation "ppc7450-sync" 35
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-integer" 1
- (and (eq_attr "type" "integer,insert,shift,\
- trap,var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
@@ -107,8 +108,9 @@ (define_insn_reservation "ppc7450-idiv" 23
"ppc7450_du,mciu_7450*23")
(define_insn_reservation "ppc7450-compare" 2
- (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md
index 67f3d11..f9a9fb8 100644
--- a/gcc/config/rs6000/7xx.md
+++ b/gcc/config/rs6000/7xx.md
@@ -61,8 +61,9 @@ (define_insn_reservation "ppc750-storec" 8
"ppc750_du,lsu_7xx")
(define_insn_reservation "ppc750-integer" 1
- (and (eq_attr "type" "integer,insert,shift,\
- trap,var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx")
@@ -100,8 +101,9 @@ (define_insn_reservation "ppc750-idiv" 19
"ppc750_du,iu1_7xx*19")
(define_insn_reservation "ppc750-compare" 2
- (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,(iu1_7xx|iu2_7xx)")
diff --git a/gcc/config/rs6000/8540.md b/gcc/config/rs6000/8540.md
index 578cf8e..fccddfe 100644
--- a/gcc/config/rs6000/8540.md
+++ b/gcc/config/rs6000/8540.md
@@ -84,9 +84,8 @@ (define_reservation "ppc8540_su_stage0"
;; Simple SU insns
(define_insn_reservation "ppc8540_su" 1
- (and (eq_attr "type" "integer,insert,cmp,compare,\
- delayed_compare,var_delayed_compare,fast_compare,\
- shift,trap,var_shift_rotate,cntlz,exts,isel")
+ (and (eq_attr "type" "integer,insert,cmp,compare,fast_compare,\
+ shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md
index 1bf308e..923524d 100644
--- a/gcc/config/rs6000/cell.md
+++ b/gcc/config/rs6000/cell.md
@@ -166,8 +166,9 @@ (define_insn_reservation "cell-vecstore" 1
;; Integer latency is 2 cycles
(define_insn_reservation "cell-integer" 2
- (and (ior (eq_attr "type" "integer,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
(eq_attr "cpu" "cell"))
@@ -200,17 +201,19 @@ (define_insn_reservation "cell-cmp" 1
;; add, addo, sub, subo, alter cr0, rldcli, rlwinm
(define_insn_reservation "cell-fast-cmp" 2
- (and (and (eq_attr "type" "fast_compare,delayed_compare,compare,\
- var_delayed_compare")
- (eq_attr "cpu" "cell"))
- (eq_attr "cell_micro" "not"))
+ (and (ior (eq_attr "type" "fast_compare,compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
+ (eq_attr "cpu" "cell")
+ (eq_attr "cell_micro" "not"))
"slot01,fxu_cell")
(define_insn_reservation "cell-cmp-microcoded" 9
- (and (and (eq_attr "type" "fast_compare,delayed_compare,compare,\
- var_delayed_compare")
- (eq_attr "cpu" "cell"))
- (eq_attr "cell_micro" "always"))
+ (and (ior (eq_attr "type" "fast_compare,compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
+ (eq_attr "cpu" "cell")
+ (eq_attr "cell_micro" "always"))
"slot0+slot1,fxu_cell,fxu_cell*7")
;; mulld
diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md
index 2abdfdb..26a449d 100644
--- a/gcc/config/rs6000/e300c2c3.md
+++ b/gcc/config/rs6000/e300c2c3.md
@@ -83,7 +83,9 @@ (define_reservation "ppce300c3_iu_stage0"
;; Compares can be executed either one of the IU or SRU
(define_insn_reservation "ppce300c3_cmp" 1
- (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare")
+ (and (ior (eq_attr "type" "cmp,compare,fast_compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
+ppce300c3_retire")
diff --git a/gcc/config/rs6000/e500mc.md b/gcc/config/rs6000/e500mc.md
index 580c30d..834e0d2 100644
--- a/gcc/config/rs6000/e500mc.md
+++ b/gcc/config/rs6000/e500mc.md
@@ -70,9 +70,8 @@ (define_reservation "e500mc_su_stage0"
;; Simple SU insns.
(define_insn_reservation "e500mc_su" 1
- (and (eq_attr "type" "integer,insert,cmp,compare,\
- delayed_compare,var_delayed_compare,fast_compare,\
- shift,trap,var_shift_rotate,cntlz,exts,isel")
+ (and (eq_attr "type" "integer,insert,cmp,compare,fast_compare,\
+ shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
diff --git a/gcc/config/rs6000/e500mc64.md b/gcc/config/rs6000/e500mc64.md
index 8844113..026d016 100644
--- a/gcc/config/rs6000/e500mc64.md
+++ b/gcc/config/rs6000/e500mc64.md
@@ -69,18 +69,24 @@ (define_reservation "e500mc64_su_stage0"
;; Simple SU insns.
(define_insn_reservation "e500mc64_su" 1
- (and (eq_attr "type" "integer,insert,delayed_compare,\
- shift,cntlz,exts")
+ (and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")
+ (eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
(define_insn_reservation "e500mc64_su2" 2
- (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare,trap")
+ (and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")
+ (eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
(define_insn_reservation "e500mc64_delayed" 2
- (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "var_shift" "yes")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
diff --git a/gcc/config/rs6000/e5500.md b/gcc/config/rs6000/e5500.md
index 6b257d6..edd0ef5 100644
--- a/gcc/config/rs6000/e5500.md
+++ b/gcc/config/rs6000/e5500.md
@@ -56,8 +56,9 @@ (define_reservation "e5500_sfx"
;; SFX.
(define_insn_reservation "e5500_sfx" 1
- (and (eq_attr "type" "integer,insert,delayed_compare,\
- shift,cntlz,exts")
+ (and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+ (and (eq_attr "type" "shift")
+ (eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
@@ -67,7 +68,8 @@ (define_insn_reservation "e5500_sfx2" 2
"e5500_decode,e5500_sfx")
(define_insn_reservation "e5500_delayed" 2
- (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "var_shift" "yes")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx*2")
diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md
index 52565d9..609d564 100644
--- a/gcc/config/rs6000/e6500.md
+++ b/gcc/config/rs6000/e6500.md
@@ -59,8 +59,9 @@ (define_reservation "e6500_sfx"
;; SFX.
(define_insn_reservation "e6500_sfx" 1
- (and (eq_attr "type" "integer,insert,delayed_compare,\
- shift,cntlz,exts")
+ (and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+ (and (eq_attr "type" "shift")
+ (eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
@@ -70,7 +71,8 @@ (define_insn_reservation "e6500_sfx2" 2
"e6500_decode,e6500_sfx")
(define_insn_reservation "e6500_delayed" 2
- (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "var_shift" "yes")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx*2")
diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md
index 7fe889c..f83c752 100644
--- a/gcc/config/rs6000/mpc.md
+++ b/gcc/config/rs6000/mpc.md
@@ -41,8 +41,9 @@ (define_insn_reservation "mpccore-fpload" 2
"lsu_mpc")
(define_insn_reservation "mpccore-integer" 1
- (and (eq_attr "type" "integer,insert,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "mpccore"))
"iu_mpc")
@@ -68,8 +69,9 @@ (define_insn_reservation "mpccore-idiv" 6
"mciu_mpc*6")
(define_insn_reservation "mpccore-compare" 3
- (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "mpccore"))
"iu_mpc,nothing,bpu_mpc")
diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md
index 73eac1f..6a1c108 100644
--- a/gcc/config/rs6000/power4.md
+++ b/gcc/config/rs6000/power4.md
@@ -210,8 +210,9 @@ (define_insn_reservation "power4-llsc" 11
; Integer latency is 2 cycles
(define_insn_reservation "power4-integer" 2
- (and (ior (eq_attr "type" "integer,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
(eq_attr "cpu" "power4"))
@@ -254,7 +255,9 @@ (define_insn_reservation "power4-cmp" 3
"iq_power4")
(define_insn_reservation "power4-compare" 2
- (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+ (and (ior (eq_attr "type" "compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
((iu1_power4,iu2_power4)\
diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md
index 8aa477a..4ebb6cf 100644
--- a/gcc/config/rs6000/power5.md
+++ b/gcc/config/rs6000/power5.md
@@ -166,8 +166,9 @@ (define_insn_reservation "power5-llsc" 11
; Integer latency is 2 cycles
(define_insn_reservation "power5-integer" 2
- (and (ior (eq_attr "type" "integer,shift,trap,\
- var_shift_rotate,cntlz,exts,isel,popcnt")
+ (and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel,popcnt")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
(eq_attr "cpu" "power5"))
@@ -207,7 +208,9 @@ (define_insn_reservation "power5-cmp" 3
"iq_power5")
(define_insn_reservation "power5-compare" 2
- (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+ (and (ior (eq_attr "type" "compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5,iu2_power5")
diff --git a/gcc/config/rs6000/power6.md b/gcc/config/rs6000/power6.md
index 26e17f9..b659645 100644
--- a/gcc/config/rs6000/power6.md
+++ b/gcc/config/rs6000/power6.md
@@ -238,6 +238,8 @@ (define_insn_reservation "power6-exts" 1
(define_insn_reservation "power6-shift" 1
(and (eq_attr "type" "shift")
+ (eq_attr "var_shift" "no")
+ (eq_attr "dot" "no")
(eq_attr "cpu" "power6"))
"FXU_power6")
@@ -287,7 +289,9 @@ (define_bypass 1 "power6-cntlz"
"store_data_bypass_p")
(define_insn_reservation "power6-var-rotate" 4
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift")
+ (eq_attr "var_shift" "yes")
+ (eq_attr "dot" "no")
(eq_attr "cpu" "power6"))
"FXU_power6")
@@ -349,12 +353,16 @@ (define_bypass 1 "power6-compare,\
"store_data_bypass_p")
(define_insn_reservation "power6-delayed-compare" 2 ; N/A
- (and (eq_attr "type" "delayed_compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "var_shift" "no")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-var-delayed-compare" 4
- (and (eq_attr "type" "var_delayed_compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "var_shift" "yes")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "power6"))
"FXU_power6")
diff --git a/gcc/config/rs6000/power7.md b/gcc/config/rs6000/power7.md
index 5527829..f4bd0b8 100644
--- a/gcc/config/rs6000/power7.md
+++ b/gcc/config/rs6000/power7.md
@@ -174,8 +174,9 @@ (define_insn_reservation "power7-sync" 11
; FX Unit
(define_insn_reservation "power7-integer" 1
- (and (eq_attr "type" "integer,insert,shift,trap,\
- var_shift_rotate,exts,isel,popcnt")
+ (and (ior (eq_attr "type" "integer,insert,trap,exts,isel,popcnt")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
@@ -200,7 +201,9 @@ (define_insn_reservation "power7-cmp" 1
"DU_power7,FXU_power7")
(define_insn_reservation "power7-compare" 2
- (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+ (and (ior (eq_attr "type" "compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power7"))
"DU2F_power7,FXU_power7,FXU_power7")
diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md
index 99c9ec7..2d50d4a 100644
--- a/gcc/config/rs6000/power8.md
+++ b/gcc/config/rs6000/power8.md
@@ -168,8 +168,9 @@ (define_insn_reservation "power8-sync" 1
; FX Unit
(define_insn_reservation "power8-1cyc" 1
- (and (eq_attr "type" "integer,insert,shift,trap,\
- var_shift_rotate,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert,trap,exts,isel")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
@@ -211,10 +212,11 @@ (define_insn_reservation "power8-fast-compare" 2
"DU_any_power8,FXU_power8")
; compare : rldicl./exts./etc
-; delayed_compare : rlwinm./slwi./etc
-; var_delayed_compare : rlwnm./slw./etc
+; shift with dot : rlwinm./slwi./rlwnm./slw./etc
(define_insn_reservation "power8-compare" 2
- (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
+ (and (ior (eq_attr "type" "compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power8"))
"DU_cracked_power8,FXU_power8,FXU_power8")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1c432cd..fb3c189 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -26187,7 +26187,6 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
{
case TYPE_CMP:
case TYPE_COMPARE:
- case TYPE_DELAYED_COMPARE:
case TYPE_FPCOMPARE:
case TYPE_CR_LOGICAL:
case TYPE_DELAYED_CR:
@@ -26197,6 +26196,12 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
return cost + 2;
else
break;
+ case TYPE_SHIFT:
+ if (get_attr_dot (dep_insn) == DOT_YES
+ && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
+ return cost + 2;
+ else
+ break;
default:
break;
}
@@ -26227,18 +26232,17 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
== SIGN_EXTEND_YES ? 6 : 4;
break;
}
- case TYPE_VAR_SHIFT_ROTATE:
- case TYPE_VAR_DELAYED_COMPARE:
+ case TYPE_SHIFT:
{
if (! store_data_bypass_p (dep_insn, insn))
- return 6;
+ return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
+ 6 : 3;
break;
}
case TYPE_INTEGER:
case TYPE_COMPARE:
case TYPE_FAST_COMPARE:
case TYPE_EXTS:
- case TYPE_SHIFT:
case TYPE_INSERT:
{
if (! store_data_bypass_p (dep_insn, insn))
@@ -26291,18 +26295,17 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
== SIGN_EXTEND_YES ? 6 : 4;
break;
}
- case TYPE_VAR_SHIFT_ROTATE:
- case TYPE_VAR_DELAYED_COMPARE:
+ case TYPE_SHIFT:
{
if (set_to_load_agen (dep_insn, insn))
- return 6;
+ return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
+ 6 : 3;
break;
- }
+ }
case TYPE_INTEGER:
case TYPE_COMPARE:
case TYPE_FAST_COMPARE:
case TYPE_EXTS:
- case TYPE_SHIFT:
case TYPE_INSERT:
{
if (set_to_load_agen (dep_insn, insn))
@@ -26476,7 +26479,10 @@ is_cracked_insn (rtx insn)
|| ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
&& get_attr_update (insn) == UPDATE_YES)
|| type == TYPE_DELAYED_CR
- || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
+ || type == TYPE_COMPARE
+ || (type == TYPE_SHIFT
+ && get_attr_dot (insn) == DOT_YES
+ && get_attr_var_shift (insn) == VAR_SHIFT_NO)
|| (type == TYPE_MUL
&& get_attr_dot (insn) == DOT_YES)
|| type == TYPE_DIV
@@ -27306,12 +27312,9 @@ insn_must_be_first_in_group (rtx insn)
{
case TYPE_EXTS:
case TYPE_CNTLZ:
- case TYPE_SHIFT:
- case TYPE_VAR_SHIFT_ROTATE:
case TYPE_TRAP:
case TYPE_MUL:
case TYPE_INSERT:
- case TYPE_DELAYED_COMPARE:
case TYPE_FPCOMPARE:
case TYPE_MFCR:
case TYPE_MTCR:
@@ -27322,6 +27325,12 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_LOAD_L:
case TYPE_STORE_C:
return true;
+ case TYPE_SHIFT:
+ if (get_attr_dot (insn) == DOT_NO
+ || get_attr_var_shift (insn) == VAR_SHIFT_NO)
+ return true;
+ else
+ break;
case TYPE_DIV:
if (get_attr_size (insn) == SIZE_32)
return true;
@@ -27350,8 +27359,6 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_MTCR:
case TYPE_DIV:
case TYPE_COMPARE:
- case TYPE_DELAYED_COMPARE:
- case TYPE_VAR_DELAYED_COMPARE:
case TYPE_ISYNC:
case TYPE_LOAD_L:
case TYPE_STORE_C:
@@ -27359,6 +27366,7 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_MTJMPR:
return true;
case TYPE_MUL:
+ case TYPE_SHIFT:
if (get_attr_dot (insn) == DOT_YES)
return true;
else
@@ -27391,8 +27399,6 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_MFCRF:
case TYPE_MTCR:
case TYPE_COMPARE:
- case TYPE_DELAYED_COMPARE:
- case TYPE_VAR_DELAYED_COMPARE:
case TYPE_SYNC:
case TYPE_ISYNC:
case TYPE_LOAD_L:
@@ -27401,6 +27407,12 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_MFJMPR:
case TYPE_MTJMPR:
return true;
+ case TYPE_SHIFT:
+ case TYPE_MUL:
+ if (get_attr_dot (insn) == DOT_YES)
+ return true;
+ else
+ break;
case TYPE_LOAD:
if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
|| get_attr_update (insn) == UPDATE_YES)
@@ -27453,11 +27465,8 @@ insn_must_be_last_in_group (rtx insn)
{
case TYPE_EXTS:
case TYPE_CNTLZ:
- case TYPE_SHIFT:
- case TYPE_VAR_SHIFT_ROTATE:
case TYPE_TRAP:
case TYPE_MUL:
- case TYPE_DELAYED_COMPARE:
case TYPE_FPCOMPARE:
case TYPE_MFCR:
case TYPE_MTCR:
@@ -27468,6 +27477,12 @@ insn_must_be_last_in_group (rtx insn)
case TYPE_LOAD_L:
case TYPE_STORE_C:
return true;
+ case TYPE_SHIFT:
+ if (get_attr_dot (insn) == DOT_NO
+ || get_attr_var_shift (insn) == VAR_SHIFT_NO)
+ return true;
+ else
+ break;
case TYPE_DIV:
if (get_attr_size (insn) == SIZE_32)
return true;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 0b13cfe..67113ee 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -159,13 +159,13 @@ (define_c_enum "unspecv"
;; computations.
(define_attr "type"
"integer,two,three,
- shift,var_shift_rotate,insert,
+ shift,insert,
mul,halfmul,div,
exts,cntlz,popcnt,isel,
load,store,fpload,fpstore,vecload,vecstore,
cmp,
branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
- compare,fast_compare,delayed_compare,var_delayed_compare,
+ compare,fast_compare,
cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
brinc,
@@ -205,6 +205,10 @@ (define_attr "update" "no,yes"
(const_string "yes")
(const_string "no")))
+;; Is this instruction using a shift amount from a register?
+;; This is used for shift insns.
+(define_attr "var_shift" "no,yes" (const_string "no"))
+
;; Define floating point instruction sub-types for use with Xfpu.md
(define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
@@ -236,11 +240,13 @@ (define_attr "cpu"
;; If this instruction is microcoded on the CELL processor
; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
(define_attr "cell_micro" "not,conditional,always"
- (if_then_else (ior (eq_attr "type" "compare,delayed_compare,var_shift_rotate,var_delayed_compare")
- (and (eq_attr "type" "mul")
+ (if_then_else (ior (eq_attr "type" "compare")
+ (and (eq_attr "type" "shift,mul")
(eq_attr "dot" "yes"))
(and (eq_attr "type" "load")
- (eq_attr "sign_extend" "yes")))
+ (eq_attr "sign_extend" "yes"))
+ (and (eq_attr "type" "shift")
+ (eq_attr "var_shift" "yes")))
(const_string "always")
(const_string "not")))
@@ -2936,8 +2942,9 @@ (define_insn "*andsi3_internal2_mc"
#
#
#"
- [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
+ [(set_attr "type" "fast_compare,fast_compare,fast_compare,shift,\
compare,compare,compare,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,4,4,8,8,8,8")])
(define_insn "*andsi3_internal3_mc"
@@ -2957,8 +2964,9 @@ (define_insn "*andsi3_internal3_mc"
#
#
#"
- [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
+ [(set_attr "type" "compare,fast_compare,fast_compare,shift,compare,\
compare,compare,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "8,4,4,4,8,8,8,8")])
(define_split
@@ -3017,8 +3025,9 @@ (define_insn "*andsi3_internal4"
#
#
#"
- [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
+ [(set_attr "type" "fast_compare,fast_compare,fast_compare,shift,\
compare,compare,compare,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,4,4,8,8,8,8")])
(define_insn "*andsi3_internal5_mc"
@@ -3040,8 +3049,9 @@ (define_insn "*andsi3_internal5_mc"
#
#
#"
- [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
+ [(set_attr "type" "compare,fast_compare,fast_compare,shift,compare,\
compare,compare,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "8,4,4,4,8,8,8,8")])
(define_split
@@ -3675,7 +3685,8 @@ (define_insn "*extzvsi_internal1"
operands[3] = GEN_INT (start + size);
return \"rlwinm. %4,%1,%3,%s2,31\";
}"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -3726,7 +3737,8 @@ (define_insn "*extzvsi_internal2"
operands[3] = GEN_INT (start + size);
return \"rlwinm. %0,%1,%3,%s2,31\";
}"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -3817,7 +3829,8 @@ (define_insn "rotlsi3"
"@
rlwnm %0,%1,%2,0xffffffff
rlwinm %0,%1,%h2,0xffffffff"
- [(set_attr "type" "var_shift_rotate,integer")])
+ [(set_attr "type" "shift,integer")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_64"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
@@ -3828,7 +3841,8 @@ (define_insn "*rotlsi3_64"
"@
rlwnm %0,%1,%2,0xffffffff
rlwinm %0,%1,%h2,0xffffffff"
- [(set_attr "type" "var_shift_rotate,integer")])
+ [(set_attr "type" "shift,integer")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -3842,7 +3856,9 @@ (define_insn "*rotlsi3_internal2"
rlwinm. %3,%1,%h2,0xffffffff
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -3872,7 +3888,9 @@ (define_insn "*rotlsi3_internal3"
rlwinm. %0,%1,%h2,0xffffffff
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -3899,7 +3917,8 @@ (define_insn "*rotlsi3_internal4"
"@
rlwnm %0,%1,%2,%m3,%M3
rlwinm %0,%1,%h2,%m3,%M3"
- [(set_attr "type" "var_shift_rotate,integer")])
+ [(set_attr "type" "shift,integer")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_internal5"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -3915,7 +3934,9 @@ (define_insn "*rotlsi3_internal5"
rlwinm. %4,%1,%h2,%m3,%M3
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -3951,7 +3972,9 @@ (define_insn "*rotlsi3_internal6"
rlwinm. %0,%1,%h2,%m3,%M3
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -4011,7 +4034,9 @@ (define_insn "*rotlsi3_internal8le"
rlwinm. %3,%1,%h2,0xff
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_insn "*rotlsi3_internal8be"
@@ -4028,7 +4053,9 @@ (define_insn "*rotlsi3_internal8be"
rlwinm. %3,%1,%h2,0xff
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -4082,7 +4109,9 @@ (define_insn "*rotlsi3_internal9le"
rlwinm. %0,%1,%h2,0xff
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_insn "*rotlsi3_internal9be"
@@ -4100,7 +4129,9 @@ (define_insn "*rotlsi3_internal9be"
rlwinm. %0,%1,%h2,0xff
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -4147,7 +4178,8 @@ (define_insn "*rotlsi3_internal10le"
"@
rlwnm %0,%1,%2,0xffff
rlwinm %0,%1,%h2,0xffff"
- [(set_attr "type" "var_shift_rotate,integer")])
+ [(set_attr "type" "shift,integer")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_internal10be"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
@@ -4159,7 +4191,8 @@ (define_insn "*rotlsi3_internal10be"
"@
rlwnm %0,%1,%2,0xffff
rlwinm %0,%1,%h2,0xffff"
- [(set_attr "type" "var_shift_rotate,integer")])
+ [(set_attr "type" "shift,integer")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_internal11le"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -4175,7 +4208,9 @@ (define_insn "*rotlsi3_internal11le"
rlwinm. %3,%1,%h2,0xffff
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_insn "*rotlsi3_internal11be"
@@ -4192,7 +4227,9 @@ (define_insn "*rotlsi3_internal11be"
rlwinm. %3,%1,%h2,0xffff
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -4246,7 +4283,9 @@ (define_insn "*rotlsi3_internal12le"
rlwinm. %0,%1,%h2,0xffff
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_insn "*rotlsi3_internal12be"
@@ -4264,7 +4303,9 @@ (define_insn "*rotlsi3_internal12be"
rlwinm. %0,%1,%h2,0xffff
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -4309,7 +4350,8 @@ (define_insn "ashlsi3"
"@
slw %0,%1,%2
slwi %0,%1,%h2"
- [(set_attr "type" "var_shift_rotate,shift")])
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*ashlsi3_64"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
@@ -4320,7 +4362,8 @@ (define_insn "*ashlsi3_64"
"@
slw %0,%1,%2
slwi %0,%1,%h2"
- [(set_attr "type" "var_shift_rotate,shift")])
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -4334,7 +4377,9 @@ (define_insn ""
slwi. %3,%1,%h2
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -4364,7 +4409,9 @@ (define_insn ""
slwi. %0,%1,%h2
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -4402,7 +4449,8 @@ (define_insn ""
"@
rlwinm. %4,%1,%h2,%m3,%M3
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -4435,7 +4483,8 @@ (define_insn ""
"@
rlwinm. %0,%1,%h2,%m3,%M3
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -4464,7 +4513,8 @@ (define_insn "lshrsi3"
mr %0,%1
srw %0,%1,%2
srwi %0,%1,%h2"
- [(set_attr "type" "integer,var_shift_rotate,shift")])
+ [(set_attr "type" "integer,shift,shift")
+ (set_attr "var_shift" "no,yes,no")])
(define_insn "*lshrsi3_64"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
@@ -4475,7 +4525,8 @@ (define_insn "*lshrsi3_64"
"@
srw %0,%1,%2
srwi %0,%1,%h2"
- [(set_attr "type" "var_shift_rotate,shift")])
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
@@ -4491,7 +4542,9 @@ (define_insn ""
#
#
#"
- [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "fast_compare,shift,shift,shift,shift,shift")
+ (set_attr "var_shift" "no,yes,no,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,4,8,8,8")])
(define_split
@@ -4523,7 +4576,9 @@ (define_insn ""
#
#
#"
- [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "fast_compare,shift,shift,shift,shift,shift")
+ (set_attr "var_shift" "no,yes,no,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,4,8,8,8")])
(define_split
@@ -4561,7 +4616,8 @@ (define_insn ""
"@
rlwinm. %4,%1,%s2,%m3,%M3
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -4594,7 +4650,8 @@ (define_insn ""
"@
rlwinm. %0,%1,%s2,%m3,%M3
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -4645,7 +4702,8 @@ (define_insn "*lshiftrt_internal2le"
"@
rlwinm. %3,%1,%s2,0xff
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_insn "*lshiftrt_internal2be"
@@ -4661,7 +4719,8 @@ (define_insn "*lshiftrt_internal2be"
"@
rlwinm. %3,%1,%s2,0xff
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -4716,7 +4775,8 @@ (define_insn "*lshiftrt_internal3le"
"@
rlwinm. %0,%1,%s2,0xff
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_insn "*lshiftrt_internal3be"
@@ -4733,7 +4793,8 @@ (define_insn "*lshiftrt_internal3be"
"@
rlwinm. %0,%1,%s2,0xff
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -4803,7 +4864,8 @@ (define_insn "*lshiftrt_internal5le"
"@
rlwinm. %3,%1,%s2,0xffff
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_insn "*lshiftrt_internal5be"
@@ -4819,7 +4881,8 @@ (define_insn "*lshiftrt_internal5be"
"@
rlwinm. %3,%1,%s2,0xffff
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -4874,7 +4937,8 @@ (define_insn "*lshiftrt_internal5le"
"@
rlwinm. %0,%1,%s2,0xffff
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_insn "*lshiftrt_internal5be"
@@ -4891,7 +4955,8 @@ (define_insn "*lshiftrt_internal5be"
"@
rlwinm. %0,%1,%s2,0xffff
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -4938,7 +5003,8 @@ (define_insn "ashrsi3"
"@
sraw %0,%1,%2
srawi %0,%1,%h2"
- [(set_attr "type" "var_shift_rotate,shift")])
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*ashrsi3_64"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
@@ -4949,7 +5015,8 @@ (define_insn "*ashrsi3_64"
"@
sraw %0,%1,%2
srawi %0,%1,%h2"
- [(set_attr "type" "var_shift_rotate,shift")])
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -4963,7 +5030,9 @@ (define_insn ""
srawi. %3,%1,%h2
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -4993,7 +5062,9 @@ (define_insn ""
srawi. %0,%1,%h2
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
\f
;; Builtins to replace a division to generate FRE reciprocal estimate
@@ -6877,7 +6948,8 @@ (define_insn "rotldi3"
"@
rldcl %0,%1,%2,0
rldicl %0,%1,%H2,0"
- [(set_attr "type" "var_shift_rotate,integer")])
+ [(set_attr "type" "shift,integer")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -6891,7 +6963,9 @@ (define_insn "*rotldi3_internal2"
rldicl. %3,%1,%H2,0
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -6921,7 +6995,9 @@ (define_insn "*rotldi3_internal3"
rldicl. %0,%1,%H2,0
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -6948,7 +7024,8 @@ (define_insn "*rotldi3_internal4"
"@
rldc%B3 %0,%1,%2,%S3
rldic%B3 %0,%1,%H2,%S3"
- [(set_attr "type" "var_shift_rotate,integer")])
+ [(set_attr "type" "shift,integer")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal5"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -6964,7 +7041,9 @@ (define_insn "*rotldi3_internal5"
rldic%B3. %4,%1,%H2,%S3
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -7000,7 +7079,9 @@ (define_insn "*rotldi3_internal6"
rldic%B3. %0,%1,%H2,%S3
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -7030,7 +7111,8 @@ (define_insn "*rotldi3_internal7le"
"@
rldcl %0,%1,%2,56
rldicl %0,%1,%H2,56"
- [(set_attr "type" "var_shift_rotate,integer")])
+ [(set_attr "type" "shift,integer")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal7be"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
@@ -7042,7 +7124,8 @@ (define_insn "*rotldi3_internal7be"
"@
rldcl %0,%1,%2,56
rldicl %0,%1,%H2,56"
- [(set_attr "type" "var_shift_rotate,integer")])
+ [(set_attr "type" "shift,integer")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal8le"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -7058,7 +7141,9 @@ (define_insn "*rotldi3_internal8le"
rldicl. %3,%1,%H2,56
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_insn "*rotldi3_internal8be"
@@ -7075,7 +7160,9 @@ (define_insn "*rotldi3_internal8be"
rldicl. %3,%1,%H2,56
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -7129,7 +7216,9 @@ (define_insn "*rotldi3_internal9le"
rldicl. %0,%1,%H2,56
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_insn "*rotldi3_internal9be"
@@ -7147,7 +7236,9 @@ (define_insn "*rotldi3_internal9be"
rldicl. %0,%1,%H2,56
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -7194,7 +7285,8 @@ (define_insn "*rotldi3_internal10le"
"@
rldcl %0,%1,%2,48
rldicl %0,%1,%H2,48"
- [(set_attr "type" "var_shift_rotate,integer")])
+ [(set_attr "type" "shift,integer")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal10be"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
@@ -7206,7 +7298,8 @@ (define_insn "*rotldi3_internal10be"
"@
rldcl %0,%1,%2,48
rldicl %0,%1,%H2,48"
- [(set_attr "type" "var_shift_rotate,integer")])
+ [(set_attr "type" "shift,integer")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal11le"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -7222,7 +7315,9 @@ (define_insn "*rotldi3_internal11le"
rldicl. %3,%1,%H2,48
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_insn "*rotldi3_internal11be"
@@ -7239,7 +7334,9 @@ (define_insn "*rotldi3_internal11be"
rldicl. %3,%1,%H2,48
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -7293,7 +7390,9 @@ (define_insn "*rotldi3_internal12le"
rldicl. %0,%1,%H2,48
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_insn "*rotldi3_internal12be"
@@ -7311,7 +7410,9 @@ (define_insn "*rotldi3_internal12be"
rldicl. %0,%1,%H2,48
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -7358,7 +7459,8 @@ (define_insn "*rotldi3_internal13le"
"@
rldcl %0,%1,%2,32
rldicl %0,%1,%H2,32"
- [(set_attr "type" "var_shift_rotate,integer")])
+ [(set_attr "type" "shift,integer")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal13be"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
@@ -7370,7 +7472,8 @@ (define_insn "*rotldi3_internal13be"
"@
rldcl %0,%1,%2,32
rldicl %0,%1,%H2,32"
- [(set_attr "type" "var_shift_rotate,integer")])
+ [(set_attr "type" "shift,integer")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal14le"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -7386,7 +7489,9 @@ (define_insn "*rotldi3_internal14le"
rldicl. %3,%1,%H2,32
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_insn "*rotldi3_internal14be"
@@ -7403,7 +7508,9 @@ (define_insn "*rotldi3_internal14be"
rldicl. %3,%1,%H2,32
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -7457,7 +7564,9 @@ (define_insn "*rotldi3_internal15le"
rldicl. %0,%1,%H2,32
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_insn "*rotldi3_internal15be"
@@ -7475,7 +7584,9 @@ (define_insn "*rotldi3_internal15be"
rldicl. %0,%1,%H2,32
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -7527,7 +7638,8 @@ (define_insn "*ashldi3_internal1"
"@
sld %0,%1,%2
sldi %0,%1,%H2"
- [(set_attr "type" "var_shift_rotate,shift")])
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*ashldi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -7541,7 +7653,9 @@ (define_insn "*ashldi3_internal2"
sldi. %3,%1,%H2
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -7571,7 +7685,9 @@ (define_insn "*ashldi3_internal3"
sldi. %0,%1,%H2
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -7756,7 +7872,8 @@ (define_insn "*lshrdi3_internal1"
"@
srd %0,%1,%2
srdi %0,%1,%H2"
- [(set_attr "type" "var_shift_rotate,shift")])
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*lshrdi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -7770,7 +7887,9 @@ (define_insn "*lshrdi3_internal2"
srdi. %3,%1,%H2
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -7800,7 +7919,9 @@ (define_insn "*lshrdi3_internal3"
srdi. %0,%1,%H2
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -7844,7 +7965,8 @@ (define_insn "*ashrdi3_internal1"
"@
srad %0,%1,%2
sradi %0,%1,%H2"
- [(set_attr "type" "var_shift_rotate,shift")])
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no")])
(define_insn "*ashrdi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -7858,7 +7980,9 @@ (define_insn "*ashrdi3_internal2"
sradi. %3,%1,%H2
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -7888,7 +8012,9 @@ (define_insn "*ashrdi3_internal3"
sradi. %0,%1,%H2
#
#"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "var_shift" "yes,no,yes,no")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -7995,9 +8121,10 @@ (define_insn "*anddi3_internal2_mc"
#
#
#"
- [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
+ [(set_attr "type" "fast_compare,compare,shift,fast_compare,\
fast_compare,compare,compare,compare,compare,compare,\
compare,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
(define_split
@@ -8048,9 +8175,10 @@ (define_insn "*anddi3_internal3_mc"
#
#
#"
- [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
+ [(set_attr "type" "fast_compare,compare,shift,fast_compare,\
fast_compare,compare,compare,compare,compare,compare,\
compare,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
(define_split
@@ -13068,7 +13196,8 @@ (define_insn ""
"@
mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "8,16")])
(define_split
@@ -13149,7 +13278,8 @@ (define_insn ""
return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
}"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "8,16")])
(define_split
diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md
index 0260a1c..82ace4a 100644
--- a/gcc/config/rs6000/rs64.md
+++ b/gcc/config/rs6000/rs64.md
@@ -46,8 +46,9 @@ (define_insn_reservation "rs64a-llsc" 2
"lsu_rs64")
(define_insn_reservation "rs64a-integer" 1
- (and (eq_attr "type" "integer,insert,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "rs64a"))
"iu_rs64")
@@ -98,8 +99,9 @@ (define_insn_reservation "rs64a-ldiv" 66
"mciu_rs64*66")
(define_insn_reservation "rs64a-compare" 3
- (and (eq_attr "type" "cmp,fast_compare,compare,\
- delayed_compare,var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "rs64a"))
"iu_rs64,nothing,bpu_rs64")
diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md
index 1d33c0f..7443d7c 100644
--- a/gcc/config/rs6000/titan.md
+++ b/gcc/config/rs6000/titan.md
@@ -51,7 +51,7 @@ (define_insn_reservation "titan_mulhw" 4
(define_bypass 2 "titan_mulhw" "titan_mulhw")
(define_insn_reservation "titan_fxu_shift_and_rotate" 2
- (and (eq_attr "type" "insert,shift,var_shift_rotate,cntlz")
+ (and (eq_attr "type" "insert,shift,cntlz")
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing*2,titan_fxu_wb")
--
1.8.1.4
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/9] rs6000: Clean up the "type" attribute
2014-05-23 6:13 [PATCH 1/9] rs6000: Clean up the "type" attribute Segher Boessenkool
` (7 preceding siblings ...)
2014-05-23 6:57 ` [PATCH 6/9] rs6000: Make all shift instructions one type Segher Boessenkool
@ 2014-05-23 13:36 ` David Edelsohn
8 siblings, 0 replies; 20+ messages in thread
From: David Edelsohn @ 2014-05-23 13:36 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Fri, May 23, 2014 at 2:09 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> Get rid of the one huge line. Group and order things a bit. Further
> changes will follow so this doesn't try to make it perfect.
>
> The rest of this patch series reduces the number of different integer
> instruction types by folding many together using attributes "size"
> (the data size), "dot" (does this instruction set CR0), and "var_shift"
> (for shift instructions: is the shift amount from a register).
>
> Many scheduling descriptions are incomplete; many instruction patterns
> use the wrong instruction type. Hopefully things will be better if
> there aren't that many different types to handle.
>
> Each patch bootstrapped on powerpc64-linux, tested with
> -m64,-m64/-mtune=power8,-m32,-m32/-mpowerpc64; no regressions (and
> nothing magically fixed either).
>
> Okay to apply?
>
>
> Segher
>
>
> 2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
>
> gcc/
> * config/rs6000/rs6000.md (type): Reorder, reformat.
Okay.
thanks, David
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 2/9] rs6000: New type attribute value "halfmul"
2014-05-23 6:13 ` [PATCH 2/9] rs6000: New type attribute value "halfmul" Segher Boessenkool
@ 2014-05-23 13:37 ` David Edelsohn
0 siblings, 0 replies; 20+ messages in thread
From: David Edelsohn @ 2014-05-23 13:37 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Fri, May 23, 2014 at 2:09 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> This is for the legacy integer multiply-accumulate instructions.
> Quite a mouthful, and "mulhw" is also a terrible name since we already
> have a machine instruction called exactly that. Hence "halfmul".
>
> Also fixes the titan automaton description for this.
>
>
> 2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
>
> gcc/
> * config/rs6000/rs6000.md (type): Add new value "halfmul".
> (*macchwc, *macchw, *macchwuc, *macchwu, *machhwc, *machhw,
> *machhwuc, *machhwu, *maclhwc, *maclhw, *maclhwuc, *maclhwu,
> *nmacchwc, *nmacchw, *nmachhwc, *nmachhw, *nmaclhwc, *nmaclhw,
> *mulchwc, *mulchw, *mulchwuc, *mulchwu, *mulhhwc, *mulhhw,
> *mulhhwuc, *mulhhwu, *mullhwc, *mullhw, *mullhwuc, *mullhwu):
> Use it.
> * config/rs6000/40x.md (ppc405-imul3): Add type halfmul.
> * config/rs6000/440.md (ppc440-imul2): Add type halfmul.
> * config/rs6000/476.md (ppc476-imul): Add type halfmul.
> * config/rs6000/titan.md: Delete nonsensical comment.
> (titan_imul): Add type imul3.
> (titan_mulhw): Remove type imul3; add type halfmul.
Okay.
thanks, David
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/9] rs6000: Make all multiply instructions one type
2014-05-23 6:13 ` [PATCH 3/9] rs6000: Make all multiply " Segher Boessenkool
@ 2014-05-23 13:40 ` David Edelsohn
2014-05-23 16:23 ` Pat Haugen
1 sibling, 0 replies; 20+ messages in thread
From: David Edelsohn @ 2014-05-23 13:40 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Fri, May 23, 2014 at 2:09 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> This uses the attributes "size" and "dot" to specify the differences:
>
> imul3 -> mul size=8
> imul2 -> mul size=16
> imul -> mul size=32
> lmul -> mul size=64
> imul_compare -> mul size=32 dot=yes
> lmul_compare -> mul size=64 dot=yes
>
>
> 2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
>
> gcc/
> * config/rs6000/rs6000.md (type): Add "mul". Delete "imul",
> "imul2", "imul3", "lmul", "imul_compare", "lmul_compare".
> (size): New attribute.
> (dot): New attribute.
> (cell_micro): Adjust.
> (mulsi3, *mulsi3_internal1, *mulsi3_internal2, mulsidi3,
> umulsidi3, smulsi3_highpart, umulsi3_highpart, muldi3,
> *muldi3_internal1, *muldi3_internal2, smuldi3_highpart,
> umuldi3_highpart): Adjust.
> * config/rs6000/rs6000.c (rs6000_adjust_cost, is_cracked_insn,
> rs6000_adjust_priority, is_nonpipeline_insn,
> insn_must_be_first_in_group, insn_must_be_last_in_group): Adjust.
>
> * config/rs6000/40x.md (ppc403-imul, ppc405-imul, ppc405-imul2,
> ppc405-imul3): Adjust.
> * config/rs6000/440.md (ppc440-imul, ppc440-imul2): Adjust.
> * config/rs6000/476.md (ppc476-imul): Adjust.
> * config/rs6000/601.md (ppc601-imul): Adjust.
> * config/rs6000/603.md (ppc603-imul, ppc603-imul2): Adjust.
> * config/rs6000/6xx.md (ppc604-imul, ppc604e-imul, ppc620-imul,
> ppc620-imul2, ppc620-imul3, ppc620-lmul): Adjust.
> * config/rs6000/7450.md (ppc7450-imul, ppc7450-imul2): Adjust.
> * config/rs6000/7xx.md (ppc750-imul, ppc750-imul2, ppc750-imul3):
> Adjust.
> * config/rs6000/8540.md (ppc8540_multiply): Adjust.
> * config/rs6000/a2.md (ppca2-imul, ppca2-lmul): Adjust.
> * config/rs6000/cell.md (cell-lmul, cell-lmul-cmp, cell-imul23,
> cell-imul): Adjust.
> * config/rs6000/e300c2c3.md (ppce300c3_multiply): Adjust.
> * config/rs6000/e500mc.md (e500mc_multiply): Adjust.
> * config/rs6000/e500mc64.md (e500mc64_multiply): Adjust.
> * config/rs6000/e5500.md (e5500_multiply, e5500_multiply_i): Adjust.
> * config/rs6000/e6500.md (e6500_multiply, e6500_multiply_i): Adjust.
> * config/rs6000/mpc.md (mpccore-imul): Adjust.
> * config/rs6000/power4.md (power4-lmul-cmp, power4-imul-cmp,
> power4-lmul, power4-imul, power4-imul3): Adjust.
> * config/rs6000/power5.md (power5-lmul-cmp, power5-imul-cmp,
> power5-lmul, power5-imul, power5-imul3): Adjust.
> * config/rs6000/power6.md (power6-lmul-cmp, power6-imul-cmp,
> power6-lmul, power6-imul, power6-imul3): Adjust.
> * config/rs6000/power7.md (power7-mul, power7-mul-compare): Adjust.
> * config/rs6000/power8.md (power8-mul, power8-mul-compare): Adjust.
>
> * config/rs6000/rs64.md (rs64a-imul, rs64a-imul2, rs64a-imul3,
> rs64a-lmul): Adjust.
> * config/rs6000/titan.md (titan_imul): Adjust.
Okay.
thanks, David
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/9] rs6000: Make all insert instructions one type
2014-05-23 6:13 ` [PATCH 4/9] rs6000: Make all insert instructions one type Segher Boessenkool
@ 2014-05-23 13:42 ` David Edelsohn
0 siblings, 0 replies; 20+ messages in thread
From: David Edelsohn @ 2014-05-23 13:42 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Fri, May 23, 2014 at 2:09 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> This uses the attribute "size" to specify the differences:
>
> insert_word -> insert size=32
> insert_dword -> insert size=64
>
> It could use "dot" as well, but the current code doesn't handle that.
>
>
> 2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
>
> gcc/
> * config/rs6000/rs6000.md (type): Delete "insert_word",
> "insert_dword". Add "insert".
> (size): Update comment.
> * config/rs6000/rs6000.c (rs6000_adjust_cost, is_cracked_insn,
> insn_must_be_first_in_group): Adjust.
> (insvsi_internal, *insvsi_internal1, *insvsi_internal2,
> *insvsi_internal3, *insvsi_internal4, *insvsi_internal5,
> *insvsi_internal6, insvdi_internal): Adjust.
>
> * config/rs6000/40x.md (ppc403-integer): Adjust.
> * config/rs6000/440.md (ppc440-integer): Adjust.
> * config/rs6000/476.md (ppc476-simple-integer): Adjust.
> * config/rs6000/601.md (ppc601-integer): Adjust.
> * config/rs6000/603.md (ppc603-integer): Adjust.
> * config/rs6000/6xx.md (ppc604-integer): Adjust.
> * config/rs6000/7450.md (ppc7450-integer): Adjust.
> * config/rs6000/7xx.md (ppc750-integer): Adjust.
> * config/rs6000/8540.md (ppc8540_su): Adjust.
> * config/rs6000/cell.md (cell-integer, cell-insert): Adjust.
> * config/rs6000/e300c2c3.md (ppce300c3_iu): Adjust.
> * config/rs6000/e500mc.md (e500mc_su): Adjust.
> * config/rs6000/e500mc64.md (e500mc64_su): Adjust.
> * config/rs6000/e5500.md (e5500_sfx): Adjust.
> * config/rs6000/e6500.md (e6500_sfx): Adjust.
> * config/rs6000/mpc.md (mpccore-integer): Adjust.
> * config/rs6000/power4.md (power4-integer, power4-insert): Adjust.
> * config/rs6000/power5.md (power5-integer, power5-insert): Adjust.
> * config/rs6000/power6.md (power6-insert, power6-insert-dword):
> Adjust.
> * config/rs6000/power7.md (power7-integer): Adjust.
> * config/rs6000/power8.md (power8-1cyc): Adjust.
> * config/rs6000/rs64.md (rs64a-integer): Adjust.
> * config/rs6000/titan.md (titan_fxu_shift_and_rotate): Adjust.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 6/9] rs6000: Make all shift instructions one type
2014-05-23 6:57 ` [PATCH 6/9] rs6000: Make all shift instructions one type Segher Boessenkool
@ 2014-05-23 13:43 ` David Edelsohn
0 siblings, 0 replies; 20+ messages in thread
From: David Edelsohn @ 2014-05-23 13:43 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Fri, May 23, 2014 at 2:09 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> This uses the attributes "var_shift" and "dot" to specify the differences:
>
> var_shift_rotate -> shift var_shift=yes
> delayed_compare -> shift var_shift=no dot=yes
> var_delayed_compare -> shift var_shift=yes dot=yes
>
>
> 2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
>
> gcc/
> * config/rs6000/rs6000.md (type): Delete "var_shift_rotate",
> "delayed_compare", "var_delayed_compare".
> (var_shift): New attribute.
> (cell_micro): Adjust.
> (*andsi3_internal2_mc, *andsi3_internal3_mc, *andsi3_internal4,
> *andsi3_internal5_mc, *extzvsi_internal1, *extzvsi_internal2,
> rotlsi3, *rotlsi3_64, *rotlsi3_internal2, *rotlsi3_internal3,
> *rotlsi3_internal4, *rotlsi3_internal5, *rotlsi3_internal6,
> *rotlsi3_internal8le, *rotlsi3_internal8be, *rotlsi3_internal9le,
> *rotlsi3_internal9be, *rotlsi3_internal10le, *rotlsi3_internal10be,
> *rotlsi3_internal11le, *rotlsi3_internal11be, *rotlsi3_internal12le,
> *rotlsi3_internal12be, ashlsi3, *ashlsi3_64, lshrsi3, *lshrsi3_64,
> *lshiftrt_internal2le, *lshiftrt_internal2be, *lshiftrt_internal3le,
> *lshiftrt_internal3be, *lshiftrt_internal5le, *lshiftrt_internal5be,
> *lshiftrt_internal5le, *lshiftrt_internal5be, ashrsi3, *ashrsi3_64,
> rotldi3, *rotldi3_internal2, *rotldi3_internal3, *rotldi3_internal4,
> *rotldi3_internal5, *rotldi3_internal6, *rotldi3_internal7le,
> *rotldi3_internal7be, *rotldi3_internal8le, *rotldi3_internal8be,
> *rotldi3_internal9le, *rotldi3_internal9be, *rotldi3_internal10le,
> *rotldi3_internal10be, *rotldi3_internal11le, *rotldi3_internal11be,
> *rotldi3_internal12le, *rotldi3_internal12be, *rotldi3_internal13le,
> *rotldi3_internal13be, *rotldi3_internal14le, *rotldi3_internal14be,
> *rotldi3_internal15le, *rotldi3_internal15be, *ashldi3_internal1,
> *ashldi3_internal2, *ashldi3_internal3, *lshrdi3_internal1,
> *lshrdi3_internal2, *lshrdi3_internal3, *ashrdi3_internal1,
> *ashrdi3_internal2, *ashrdi3_internal3, *anddi3_internal2_mc,
> *anddi3_internal3_mc, as well as 11 anonymous define_insns): Adjust.
> * config/rs6000/rs6000.c (rs6000_adjust_cost, is_cracked_insn,
> insn_must_be_first_in_group, insn_must_be_last_in_group): Adjust.
>
> * config/rs6000/40x.md (ppc403-integer, ppc403-compare): Adjust.
> * config/rs6000/440.md (ppc440-integer): Adjust.
> * config/rs6000/476.md (ppc476-simple-integer, ppc476-compare):
> Adjust.
> * config/rs6000/601.md (ppc601-integer, ppc601-compare): Adjust.
> * config/rs6000/603.md (ppc603-integer, ppc603-compare): Adjust.
> * config/rs6000/6xx.md (ppc604-integer, ppc604-compare): Adjust.
> * config/rs6000/7450.md (ppc7450-integer, ppc7450-compare):
> Adjust.
> * config/rs6000/7xx.md (ppc750-integer, ppc750-compare): Adjust.
> * config/rs6000/8540.md (ppc8540_su): Adjust.
> * config/rs6000/cell.md (cell-integer, cell-fast-cmp,
> cell-cmp-microcoded): Adjust.
> * config/rs6000/e300c2c3.md (ppce300c3_cmp): Adjust.
> * config/rs6000/e500mc.md (e500mc_su): Adjust.
> * config/rs6000/e500mc64.md (e500mc64_su, e500mc64_su2,
> e500mc64_delayed): Adjust.
> * config/rs6000/e5500.md (e5500_sfx, e5500_delayed): Adjust.
> * config/rs6000/e6500.md (e6500_sfx, e6500_delayed): Adjust.
> * config/rs6000/mpc.md (mpccore-integer, mpccore-compare): Adjust.
> * config/rs6000/power4.md (power4-integer, power4-compare):
> Adjust.
> * config/rs6000/power5.md (power5-integer, power5-compare):
> Adjust.
> * config/rs6000/power6.md (power6-shift, power6-var-rotate,
> power6-delayed-compare, power6-var-delayed-compare): Adjust.
> * config/rs6000/power7.md (power7-integer, power7-compare):
> Adjust.
> * config/rs6000/power8.md (power8-1cyc, power8-compare): Adjust.
> Adjust comment.
> * config/rs6000/rs64.md (rs64a-integer, rs64a-compare): Adjust.
> * config/rs6000/titan.md (titan_fxu_shift_and_rotate): Adjust.
Okay.
thanks, David
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 7/9] rs6000: Make all add instructions one type
2014-05-23 6:56 ` [PATCH 7/9] rs6000: Make all add " Segher Boessenkool
@ 2014-05-23 13:45 ` David Edelsohn
0 siblings, 0 replies; 20+ messages in thread
From: David Edelsohn @ 2014-05-23 13:45 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Fri, May 23, 2014 at 2:09 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> They are currently just "integer", but the dot version is fast_compare.
> This makes them all "add". Later we should introduce attributes to
> distinguish e.g. addc and adde (which aren't currently handled as
> separate instructions at all, only in groups).
>
>
> 2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
>
> gcc/
> * config/rs6000/rs6000.md (type): Add "add".
> (*add<mode>3_internal1, addsi3_high, *add<mode>3_internal2,
> *add<mode>3_internal3, *neg<mode>2_internal, and 5 anonymous
> define_insns): Use it.
> * config/rs6000/rs6000.c (rs6000_adjust_cost): Adjust.
>
> * config/rs6000/40x.md (ppc403-integer, ppc403-compare): Adjust.
> * config/rs6000/440.md (ppc440-integer, ppc440-compare): Adjust.
> * config/rs6000/476.md (ppc476-simple-integer, ppc476-compare):
> Adjust.
> * config/rs6000/601.md (ppc601-integer): Adjust.
> * config/rs6000/603.md (ppc603-integer, ppc603-compare): Adjust.
> * config/rs6000/6xx.md (ppc604-integer, ppc604-compare): Adjust.
> * config/rs6000/7450.md (ppc7450-integer, ppc7450-compare): Adjust.
> * config/rs6000/7xx.md (ppc750-integer, ppc750-compare): Adjust.
> * config/rs6000/8540.md (ppc8540_su): Adjust.
> * config/rs6000/cell.md (cell-integer, cell-fast-cmp,
> cell-cmp-microcoded): Adjust.
> * config/rs6000/e300c2c3.md (ppce300c3_cmp, ppce300c3_iu): Adjust.
> * config/rs6000/e500mc.md (e500mc_su): Adjust.
> * config/rs6000/e500mc64.md (e500mc64_su, e500mc64_su2): Adjust.
> * config/rs6000/e5500.md (e5500_sfx, e5500_sfx2): Adjust.
> * config/rs6000/e6500.md (e6500_sfx, e6500_sfx2): Adjust.
> * config/rs6000/mpc.md (mpccore-integer, mpccore-compare): Adjust.
> * config/rs6000/power4.md (power4-integer, power4-cmp): Adjust.
> * config/rs6000/power5.md (power5-integer, power5-cmp): Adjust.
> * config/rs6000/power6.md (power6-integer, power6-fast-compare):
> Adjust.
> * config/rs6000/power7.md (power7-integer, power7-cmp): Adjust.
> * config/rs6000/power8.md (power8-1cyc, power8-fast-compare):
> Adjust.
> * config/rs6000/rs64.md (rs64a-integer, rs64a-compare): Adjust.
> * config/rs6000/titan.md (titan_fxu_adder, titan_fxu_alu): Adjust.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 8/9] rs6000: Make all logical instructions one type
2014-05-23 6:56 ` [PATCH 8/9] rs6000: Make all logical " Segher Boessenkool
@ 2014-05-23 13:46 ` David Edelsohn
0 siblings, 0 replies; 20+ messages in thread
From: David Edelsohn @ 2014-05-23 13:46 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Fri, May 23, 2014 at 2:09 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> They are currently just "integer", but the dot version is fast_compare.
> This makes them all "logical".
>
>
> 2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
>
> gcc/
> * config/rs6000/rs6000.md (type): Add "logical". Delete
> "fast_compare".
> (dot): Adjust comment.
> (andsi3_mc, *andsi3_internal2_mc, *andsi3_internal3_mc,
> *andsi3_internal4, *andsi3_internal5_mc, *boolsi3_internal2,
> *boolsi3_internal3, *boolccsi3_internal2, *boolccsi3_internal3,
> anddi3_mc, *anddi3_internal2_mc, *anddi3_internal3_mc,
> *booldi3_internal2, *booldi3_internal3, *boolcdi3_internal2,
> *boolcdi3_internal3, *boolccdi3_internal2, *boolccdi3_internal3,
> *mov<mode>_internal2, and 10 anonymous define_insns): Use
> "logical".
> * config/rs6000/rs6000.c (rs6000_adjust_cost): Adjust.
>
> * config/rs6000/40x.md: (ppc403-integer, ppc403-compare): Adjust.
> * config/rs6000/440.md: (ppc440-integer, ppc440-compare): Adjust.
> * config/rs6000/476.md: (ppc476-simple-integer, ppc476-compare):
> Adjust.
> * config/rs6000/603.md: (ppc603-integer, ppc603-compare): Adjust.
> * config/rs6000/6xx.md: (ppc604-integer, ppc604-compare): Adjust.
> * config/rs6000/7450.md: (ppc7450-integer, ppc7450-compare):
> Adjust.
> * config/rs6000/7xx.md: (ppc750-integer, ppc750-compare): Adjust.
> * config/rs6000/8540.md: (ppc8540_su): Adjust.
> * config/rs6000/cell.md: (cell-integer, cell-fast-cmp,
> cell-cmp-microcoded): Adjust.
> * config/rs6000/e300c2c3.md: (ppce300c3_cmp, ppce300c3_iu):
> Adjust.
> * config/rs6000/e500mc.md: (e500mc_su): Adjust.
> * config/rs6000/e500mc64.md: (e500mc64_su, e500mc64_su2): Adjust.
> * config/rs6000/e5500.md: (e5500_sfx, e5500_sfx2): Adjust.
> * config/rs6000/e6500.md: (e6500_sfx, e6500_sfx2): Adjust.
> * config/rs6000/mpc.md: (mpccore-integer, mpccore-compare):
> Adjust.
> * config/rs6000/power4.md: (power4-integer, power4-cmp): Adjust.
> * config/rs6000/power5.md: (power5-integer, power5-cmp): Adjust.
> * config/rs6000/power6.md: (power6-integer, power6-fast-compare):
> Adjust.
> * config/rs6000/power7.md: (power7-integer, power7-cmp): Adjust.
> * config/rs6000/power8.md: (power8-1cyc, power8-fast-compare):
> Adjust. Adjust comment.
> * config/rs6000/rs64.md: (rs64a-integer, rs64a-compare): Adjust.
> * config/rs6000/titan.md: (titan_fxu_adder, titan_fxu_alu):
> Adjust.
Okay.
thanks, David
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/9] rs6000: Make all divide instructions one type
2014-05-23 6:56 ` [PATCH 5/9] rs6000: Make all divide " Segher Boessenkool
@ 2014-05-23 13:46 ` David Edelsohn
0 siblings, 0 replies; 20+ messages in thread
From: David Edelsohn @ 2014-05-23 13:46 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Fri, May 23, 2014 at 2:09 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> This uses the attribute "size" to specify the differences:
>
> idiv -> div size=32
> ldiv -> div size=64
>
> It could use "dot" as well, but the current code doesn't handle that.
>
>
> 2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
>
> gcc/
> * config/rs6000/rs6000.md (type): Delete "idiv", "ldiv". Add
> "div".
> (bits): New mode_attr.
> (idiv_ldiv): Delete mode_attr.
> (udiv<mode>3, *div<mode>3, div<div_extend>_<mode>): Adjust.
> * config/rs6000/rs6000.c (rs6000_adjust_cost, is_cracked_insn,
> rs6000_adjust_priority, is_nonpipeline_insn,
> insn_must_be_first_in_group, insn_must_be_last_in_group): Adjust.
>
> * config/rs6000/40x.md (ppc403-idiv): Adjust.
> * config/rs6000/440.md (ppc440-idiv): Adjust.
> * config/rs6000/476.md (ppc476-idiv): Adjust.
> * config/rs6000/601.md (ppc601-idiv): Adjust.
> * config/rs6000/603.md (ppc603-idiv): Adjust.
> * config/rs6000/6xx.md (ppc604-idiv, ppc620-idiv, ppc630-idiv,
> ppc620-ldiv): Adjust.
> * config/rs6000/7450.md (ppc7450-idiv): Adjust.
> * config/rs6000/7xx.md (ppc750-idiv): Adjust.
> * config/rs6000/8540.md (ppc8540_divide): Adjust.
> * config/rs6000/a2.md (ppca2-idiv, ppca2-ldiv): Adjust.
> * config/rs6000/cell.md (cell-idiv, cell-ldiv): Adjust.
> * config/rs6000/e300c2c3.md (ppce300c3_divide): Adjust.
> * config/rs6000/e500mc.md (e500mc_divide): Adjust.
> * config/rs6000/e500mc64.md (e500mc64_divide): Adjust.
> * config/rs6000/e5500.md (e5500_divide, e5500_divide_d): Adjust.
> * config/rs6000/e6500.md (e6500_divide, e6500_divide_d): Adjust.
> * config/rs6000/mpc.md (mpccore-idiv): Adjust.
> * config/rs6000/power4.md (power4-idiv, power4-ldiv): Adjust.
> * config/rs6000/power5.md (power5-idiv, power5-ldiv): Adjust.
> * config/rs6000/power6.md (power6-idiv, power6-ldiv): Adjust.
> * config/rs6000/power7.md (power7-idiv, power7-ldiv): Adjust.
> * config/rs6000/power8.md (power8-idiv, power8-ldiv): Adjust.
> * config/rs6000/rs64.md (rs64a-idiv, rs64a-ldiv): Adjust.
> * config/rs6000/titan.md (titan_fxu_div): Adjust.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 9/9] rs6000: Make all rlw*nm and rld*c* type shift
2014-05-23 6:56 ` [PATCH 9/9] rs6000: Make all rlw*nm and rld*c* type shift Segher Boessenkool
@ 2014-05-23 13:47 ` David Edelsohn
0 siblings, 0 replies; 20+ messages in thread
From: David Edelsohn @ 2014-05-23 13:47 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: GCC Patches
On Fri, May 23, 2014 at 2:09 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> They are often labeled just "integer" currently. Fix that.
>
> Also handle shift properly in those scheduling descriptions that
> neglected it.
>
>
> 2014-05-22 Segher Boessenkool <segher@kernel.crashing.org>
>
> gcc/
> * config/rs6000/440.md (ppc440-integer): Include shift without
> dot.
> (ppc440-compare): Include shift with dot.
> * config/rs6000/e300c2c3.md (ppce300c3_iu): Include shift without
> dot.
> * config/rs6000/e5500.md (e5500_sfx2): Include constant shift
> without dot.
> * config/rs6000/e6500.md (e6500_sfx): Exclude constant shift
> without dot.
> (e6500_sfx2): Include it.
> * config/rs6000/rs6000.md ( *zero_extend<mode>di2_internal1,
> *zero_extend<mode>di2_internal2, *zero_extend<mode>di2_internal3,
> *zero_extendsidi2_lfiwzx, andsi3_mc, andsi3_nomc,
> andsi3_internal0_nomc, extzvsi_internal, extzvdi_internal,
> *extzvdi_internal1, *extzvdi_internal2, rotlsi3, *rotlsi3_64,
> *rotlsi3_internal4, *rotlsi3_internal7le, *rotlsi3_internal7be,
> *rotlsi3_internal10le, *rotlsi3_internal10be, rlwinm,
> *lshiftrt_internal1le, *lshiftrt_internal1be,
> *lshiftrt_internal4le, *lshiftrt_internal4be, rotldi3,
> *rotldi3_internal4, *rotldi3_internal7le, *rotldi3_internal7be,
> *rotldi3_internal10le, *rotldi3_internal10be,
> *rotldi3_internal13le, *rotldi3_internal13be, *ashldi3_internal4,
> ashldi3_internal5, *ashldi3_internal6, *ashldi3_internal7,
> ashldi3_internal8, *ashldi3_internal9, anddi3_mc, anddi3_nomc,
> *anddi3_internal2_mc, *anddi3_internal3_mc, and 4 anonymous
> define_insns): Use type "shift" in the appropriate alternatives.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/9] rs6000: Make all multiply instructions one type
2014-05-23 6:13 ` [PATCH 3/9] rs6000: Make all multiply " Segher Boessenkool
2014-05-23 13:40 ` David Edelsohn
@ 2014-05-23 16:23 ` Pat Haugen
2014-05-23 19:14 ` Segher Boessenkool
1 sibling, 1 reply; 20+ messages in thread
From: Pat Haugen @ 2014-05-23 16:23 UTC (permalink / raw)
To: Segher Boessenkool, gcc-patches; +Cc: dje.gcc
On 05/23/2014 01:09 AM, Segher Boessenkool wrote:
> @@ -27385,6 +27371,11 @@ insn_must_be_first_in_group (rtx insn)
> case TYPE_MFJMPR:
> case TYPE_MTJMPR:
> return true;
> + case TYPE_MUL:
> + if (get_attr_dot (insn) == DOT_YES)
> + return true;
> + else
> + break;
> case TYPE_LOAD:
> if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
> || get_attr_update (insn) == UPDATE_YES)
> @@ -27415,8 +27406,6 @@ insn_must_be_first_in_group (rtx insn)
> case TYPE_COMPARE:
> case TYPE_DELAYED_COMPARE:
> case TYPE_VAR_DELAYED_COMPARE:
> - case TYPE_IMUL_COMPARE:
> - case TYPE_LMUL_COMPARE:
> case TYPE_SYNC:
> case TYPE_ISYNC:
> case TYPE_LOAD_L:
This looks like you added it to the POWER7 case and removed from the
POWER8 case. The MUL_COMPARE types should have been listed for the
POWER7 case leg also, so the addition there is fine, but the new code
should also be duplicated in the POWER8 case leg.
-Pat
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/9] rs6000: Make all multiply instructions one type
2014-05-23 16:23 ` Pat Haugen
@ 2014-05-23 19:14 ` Segher Boessenkool
0 siblings, 0 replies; 20+ messages in thread
From: Segher Boessenkool @ 2014-05-23 19:14 UTC (permalink / raw)
To: Pat Haugen; +Cc: gcc-patches, dje.gcc
On Fri, May 23, 2014 at 11:22:10AM -0500, Pat Haugen wrote:
> On 05/23/2014 01:09 AM, Segher Boessenkool wrote:
> >@@ -27385,6 +27371,11 @@ insn_must_be_first_in_group (rtx insn)
> > case TYPE_MFJMPR:
> > case TYPE_MTJMPR:
> > return true;
> >+ case TYPE_MUL:
> >+ if (get_attr_dot (insn) == DOT_YES)
> >+ return true;
> >+ else
> >+ break;
> > case TYPE_LOAD:
> > if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
> > || get_attr_update (insn) == UPDATE_YES)
> >@@ -27415,8 +27406,6 @@ insn_must_be_first_in_group (rtx insn)
> > case TYPE_COMPARE:
> > case TYPE_DELAYED_COMPARE:
> > case TYPE_VAR_DELAYED_COMPARE:
> >- case TYPE_IMUL_COMPARE:
> >- case TYPE_LMUL_COMPARE:
> > case TYPE_SYNC:
> > case TYPE_ISYNC:
> > case TYPE_LOAD_L:
> This looks like you added it to the POWER7 case and removed from the
> POWER8 case. The MUL_COMPARE types should have been listed for the
> POWER7 case leg also, so the addition there is fine, but the new code
> should also be duplicated in the POWER8 case leg.
Looks like a mismerge/rebase. Sorry. That's what happens with huge
repetitive functions :-(
The "shift" patch adds it back for the POWER8 case. Somehow I missed
that when reviewing.
I didn't intend to change anything with these patches; will leave the
POWER7 case though since you like it.
Thanks,
Segher
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2014-05-23 19:14 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-05-23 6:13 [PATCH 1/9] rs6000: Clean up the "type" attribute Segher Boessenkool
2014-05-23 6:13 ` [PATCH 2/9] rs6000: New type attribute value "halfmul" Segher Boessenkool
2014-05-23 13:37 ` David Edelsohn
2014-05-23 6:13 ` [PATCH 4/9] rs6000: Make all insert instructions one type Segher Boessenkool
2014-05-23 13:42 ` David Edelsohn
2014-05-23 6:13 ` [PATCH 3/9] rs6000: Make all multiply " Segher Boessenkool
2014-05-23 13:40 ` David Edelsohn
2014-05-23 16:23 ` Pat Haugen
2014-05-23 19:14 ` Segher Boessenkool
2014-05-23 6:56 ` [PATCH 7/9] rs6000: Make all add " Segher Boessenkool
2014-05-23 13:45 ` David Edelsohn
2014-05-23 6:56 ` [PATCH 8/9] rs6000: Make all logical " Segher Boessenkool
2014-05-23 13:46 ` David Edelsohn
2014-05-23 6:56 ` [PATCH 5/9] rs6000: Make all divide " Segher Boessenkool
2014-05-23 13:46 ` David Edelsohn
2014-05-23 6:56 ` [PATCH 9/9] rs6000: Make all rlw*nm and rld*c* type shift Segher Boessenkool
2014-05-23 13:47 ` David Edelsohn
2014-05-23 6:57 ` [PATCH 6/9] rs6000: Make all shift instructions one type Segher Boessenkool
2014-05-23 13:43 ` David Edelsohn
2014-05-23 13:36 ` [PATCH 1/9] rs6000: Clean up the "type" attribute David Edelsohn
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