From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28851 invoked by alias); 2 Aug 2014 01:46:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 28838 invoked by uid 89); 2 Aug 2014 01:46:40 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-vc0-f170.google.com Received: from mail-vc0-f170.google.com (HELO mail-vc0-f170.google.com) (209.85.220.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Sat, 02 Aug 2014 01:46:39 +0000 Received: by mail-vc0-f170.google.com with SMTP id lf12so8005520vcb.1 for ; Fri, 01 Aug 2014 18:46:37 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.221.68.66 with SMTP id xx2mr10959179vcb.1.1406943996918; Fri, 01 Aug 2014 18:46:36 -0700 (PDT) Received: by 10.220.11.5 with HTTP; Fri, 1 Aug 2014 18:46:36 -0700 (PDT) In-Reply-To: <9ffea8b9e44144208d66d2a5795438ba@BN1PR0301MB0644.namprd03.prod.outlook.com> References: <201408011428.s71ESvBE005167@d06av02.portsmouth.uk.ibm.com> <9ffea8b9e44144208d66d2a5795438ba@BN1PR0301MB0644.namprd03.prod.outlook.com> Date: Sat, 02 Aug 2014 01:46:00 -0000 Message-ID: Subject: Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno From: David Edelsohn To: "rohitarulraj@freescale.com" Cc: Ulrich Weigand , "gcc-patches@gcc.gnu.org" , Edmar Wienskoski , Alan Modra , Jakub Jelinek Content-Type: text/plain; charset=ISO-8859-1 X-SW-Source: 2014-08/txt/msg00113.txt.bz2 On Fri, Aug 1, 2014 at 2:03 PM, rohitarulraj@freescale.com wrote: > Hello Ulrich, > > Thanks. > >> > /* Use gcc hard register numbering for eh_frame. */ -#define >> >DWARF_FRAME_REGNUM(REGNO) (REGNO) >> >+#define DWARF_FRAME_REGNUM(REGNO) \ >> >+ ((REGNO) >= FIRST_SPE_HIGH_REGNO ? ((REGNO) - >> FIRST_SPE_HIGH_REGNO + >> >+1200) : (REGNO)) >> >> Any reason for not using SPE_HIGH_REGNO_P here, just in case we do get >> other hard registers at some point? > > Yes, we can use it. I just have to move the definition of "SPE_HIGH_REGNO_P" macro before "DWARF_FRAME_REGNUM" macro definition. > [Previously, I had defined and placed "SPE_HIGH_REGNO_P" macro along with similar macros "ALTIVEC_REGNO_P" etc.] > > I had updated the patch as required (For this last change, I have checked/tested only the builds: ppc64 trunk, e500v2 v4.9.1 bareboard & linux build). > > PR target/60102 > > [libgcc] > 2014-07-31 Rohit > * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update > based on change in SPE high register numbers and 3 HTM registers. > > [gcc] > 2014-07-31 Rohit > * config/rs6000/rs6000.c > (rs6000_reg_names) : Add SPE high register names. > (alt_reg_names) : Likewise. > (rs6000_dwarf_register_span) : For SPE high registers, replace > dwarf register numbers with GCC hard register numbers. > (rs6000_init_dwarf_reg_sizes_extra) : Likewise. > (rs6000_dbx_register_number): For SPE high registers, return dwarf > register number for the corresponding GCC hard register number. > > * config/rs6000/rs6000.h > (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard > register numbers for SPE high registers. > (DWARF_FRAME_REGISTERS) : Likewise. > (DWARF_REG_TO_UNWIND_COLUMN) : Likewise. > (DWARF_FRAME_REGNUM) : Likewise. > (FIXED_REGISTERS) : Likewise. > (CALL_USED_REGISTERS) : Likewise. > (CALL_REALLY_USED_REGISTERS) : Likewise. > (REG_ALLOC_ORDER) : Likewise. > (enum reg_class) : Likewise. > (REG_CLASS_NAMES) : Likewise. > (REG_CLASS_CONTENTS) : Likewise. > (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers. > > * gcc.target/powerpc/pr60102.c: New testcase. The patch is okay with me if Uli is satisfied. Thanks, David