* [PATCH] PR59844, Fix gcc 4.9 power8 -O3 little endian direct move paterns
@ 2014-01-16 16:08 Michael Meissner
2014-01-16 16:51 ` David Edelsohn
0 siblings, 1 reply; 2+ messages in thread
From: Michael Meissner @ 2014-01-16 16:08 UTC (permalink / raw)
To: gcc-patches, dje.gcc
[-- Attachment #1: Type: text/plain, Size: 1144 bytes --]
This patch fixes the problem that was noticed when we attempted to boostrap the
compiler on a little endian power8 system with the -O3 -mcpu=power8 options.
During the development of the power8 direct move patches, I put a guard test in
the 128-bit direct move insns to make the patterns big endian only. Since I
used gen_highpart and gen_lowpart to generate the SUBREGs in the split, the
existing code is safe for little endian. This patch removes the big endian
guard tests.
This patch has been regression tested on a little endian power8 system, and it
allows the code to compile. I looked at the assembler generated, and it looks
correct. Is this patch ok to apply?
2014-01-16 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (reload_vsx_from_gprsf): Add little
endian support, remove tests for WORDS_BIG_ENDIAN.
(p8_mfvsrd_3_<mode>): Likewise.
(reload_gpr_from_vsx<mode>): Likewise.
(reload_gpr_from_vsxsf): Likewise.
(p8_mfvsrd_4_disf): Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
[-- Attachment #2: pr59844.patch01b --]
[-- Type: text/plain, Size: 2093 bytes --]
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 206643)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -9972,7 +9972,7 @@ (define_insn_and_split "reload_vsx_from_
(unspec:SF [(match_operand:SF 1 "register_operand" "r")]
UNSPEC_P8V_RELOAD_FROM_GPR))
(clobber (match_operand:DI 2 "register_operand" "=r"))]
- "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -9999,7 +9999,7 @@ (define_insn "p8_mfvsrd_3_<mode>"
[(set (match_operand:DF 0 "register_operand" "=r")
(unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
UNSPEC_P8V_RELOAD_FROM_VSX))]
- "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"mfvsrd %0,%x1"
[(set_attr "type" "mftgpr")])
@@ -10009,7 +10009,7 @@ (define_insn_and_split "reload_gpr_from_
[(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
UNSPEC_P8V_RELOAD_FROM_VSX))
(clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
- "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -10036,7 +10036,7 @@ (define_insn_and_split "reload_gpr_from_
(unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
UNSPEC_P8V_RELOAD_FROM_VSX))
(clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
- "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -10058,7 +10058,7 @@ (define_insn "p8_mfvsrd_4_disf"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
UNSPEC_P8V_RELOAD_FROM_VSX))]
- "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"mfvsrd %0,%x1"
[(set_attr "type" "mftgpr")])
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] PR59844, Fix gcc 4.9 power8 -O3 little endian direct move paterns
2014-01-16 16:08 [PATCH] PR59844, Fix gcc 4.9 power8 -O3 little endian direct move paterns Michael Meissner
@ 2014-01-16 16:51 ` David Edelsohn
0 siblings, 0 replies; 2+ messages in thread
From: David Edelsohn @ 2014-01-16 16:51 UTC (permalink / raw)
To: Michael Meissner, GCC Patches
On Thu, Jan 16, 2014 at 11:08 AM, Michael Meissner
<meissner@linux.vnet.ibm.com> wrote:
> This patch fixes the problem that was noticed when we attempted to boostrap the
> compiler on a little endian power8 system with the -O3 -mcpu=power8 options.
>
> During the development of the power8 direct move patches, I put a guard test in
> the 128-bit direct move insns to make the patterns big endian only. Since I
> used gen_highpart and gen_lowpart to generate the SUBREGs in the split, the
> existing code is safe for little endian. This patch removes the big endian
> guard tests.
>
> This patch has been regression tested on a little endian power8 system, and it
> allows the code to compile. I looked at the assembler generated, and it looks
> correct. Is this patch ok to apply?
>
> 2014-01-16 Michael Meissner <meissner@linux.vnet.ibm.com>
>
> * config/rs6000/rs6000.md (reload_vsx_from_gprsf): Add little
> endian support, remove tests for WORDS_BIG_ENDIAN.
> (p8_mfvsrd_3_<mode>): Likewise.
> (reload_gpr_from_vsx<mode>): Likewise.
> (reload_gpr_from_vsxsf): Likewise.
> (p8_mfvsrd_4_disf): Likewise.
Okay. Thanks Mike and Bill for tracking this down and testing.
Thanks, David
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2014-01-16 16:51 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-01-16 16:08 [PATCH] PR59844, Fix gcc 4.9 power8 -O3 little endian direct move paterns Michael Meissner
2014-01-16 16:51 ` David Edelsohn
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).