From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by sourceware.org (Postfix) with ESMTPS id 424063857344 for ; Fri, 29 Sep 2023 19:44:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 424063857344 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-533d31a8523so15531985a12.1 for ; Fri, 29 Sep 2023 12:44:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696016672; x=1696621472; darn=gcc.gnu.org; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :from:to:cc:subject:date:message-id:reply-to; bh=dFpVu71uff6zokW8o/oR9uSbh+mFFuCnmsTId9gvT2A=; b=Y2367TzAa3maiv3ZMJXw4ARtP7uLIsLDbinkNjSSjRs3OQDnDS5brkaEgrspCIkWpH 1rdnDEyj4pU50D4cXc5L8dTDSVSc50KpRLOfMb+SPByr4yn8PAwJX2jEnrC4xT5+2pwD z26DCdQcfbOgQF3K3NzCtyzyoT3Xr5dz6Vshnc0HEBzZ3uOoI5/OqnsgPaEJR2j+1ddv vFmw2fMTjWheKQx2zvQMfg/8caDXQmTQpcMjO2wT+pqJqNauoW+AHQ4X9mYBQ80p5wke UrKx4RTwxlJ0bgZPkeCbj0kh8r768aOojDTqr0EoobgGY8P0MOBzG8ai8z2Kf2qApUUv LUdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696016672; x=1696621472; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=dFpVu71uff6zokW8o/oR9uSbh+mFFuCnmsTId9gvT2A=; b=E6Zoe+Z3Mk3mZT/uA0oShl5pN6QobqWzDwy1M0UEJAaddcUlNxKHW7WHkIGH7Yejkv 3BHadJ/nKNp3dXzqX3/bJIzUMLxbxSlfu04Md+TMHlzrewuzP1sf/MjTv1K0whBl0J+H 35Ij4SVvi7TJ235xOCLMwtKAIScMfdfN4iPDtvqjZQBnbcO8mju/Dwws38cYEOhH/nBd HlQsz3jRmeAJrdRiKjKP10RU1AL/QUakoG3ObHCggs2udyD71w2K8SOtsQi7FK0S/huT bBnLv742yV2ltkrukWtlTbz2WQ86PukUW22vzer28YgsJEqby0959ADrJVevdhW2JiSX z14A== X-Gm-Message-State: AOJu0YzAdxauKCzHxddt0C+yTWJwN1eUgOB4s79QlQwnEdXgi7G7BzHP jIp5tUfqnAi1yV35+D6OCxJREzR6RIixDZtYAOU= X-Google-Smtp-Source: AGHT+IHzXOlbXmAzg4kTJQ2cFaICPqSbDWgV3X44MeSYHXctA8ns7c9aWgKmf2Ua9P+6qhxBQ5VBflr4AhLBYOviyzE= X-Received: by 2002:a17:906:51db:b0:9b2:abda:2543 with SMTP id v27-20020a17090651db00b009b2abda2543mr5317334ejk.65.1696016671302; Fri, 29 Sep 2023 12:44:31 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: David Edelsohn Date: Fri, 29 Sep 2023 15:44:19 -0400 Message-ID: Subject: Re: [PATCH] Cleanup: Replace UNSPEC_COPYSIGN with copysign RTL To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner Content-Type: multipart/alternative; boundary="00000000000039ea0a060684a7a9" X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000039ea0a060684a7a9 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Sep 29, 2023 at 2:09=E2=80=AFPM Michael Meissner wrote: > When I first implemented COPYSIGN support in the power7 days, we did not > have a > copysign RTL insn, so I had to use UNSPEC to represent the copysign > instruction. This patch removes those UNSPECs, and it uses the native RTL > copysign insn. > > I have tested this on both big endian and little endian PowerPC server > systems, > and there were no regressions. Can I check this into the master branch? > Since > it is just a clean-up, I don't see the need to back port it, but it is > simple > to do the back port if desired. > > 2023-09-29 Michael Meissner > > gcc/ > > * config/rs6000/rs6000.md (UNSPEC_COPYSIGN): Delete. > (copysign3_fcpsg): Use copysign RTL instead of UNSPEC. > (copysign3_hard): Likewise. > (copysign3_soft): Likewise. > * config/rs6000/vector.md (vector_copysign3): Use copysign > RTL > instead of UNSPEC. > * config/rs6000/vsx.md (vsx_copysign3): Use copysign RTL > instead > of UNSPEC. > --- > gcc/config/rs6000/rs6000.md | 20 ++++++++------------ > gcc/config/rs6000/vector.md | 4 ++-- > gcc/config/rs6000/vsx.md | 7 +++---- > 3 files changed, 13 insertions(+), 18 deletions(-) > > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md > index 7b583d7a69a..1b6b6cb5bbe 100644 > --- a/gcc/config/rs6000/rs6000.md > +++ b/gcc/config/rs6000/rs6000.md > @@ -108,7 +108,6 @@ (define_c_enum "unspec" > UNSPEC_TOCREL > UNSPEC_MACHOPIC_OFFSET > UNSPEC_BPERM > - UNSPEC_COPYSIGN > UNSPEC_PARITY > UNSPEC_CMPB > UNSPEC_FCTIW > @@ -5383,9 +5382,8 @@ (define_expand "copysign3" > ;; compiler from optimizing -0.0 > The comment above the define_insn refers to UNSPEC instead of if-then-else because of -0.0. Please remove or update the comment because the pattern no longer uses UNSPEC. The rest of the patch is okay with that change. Thanks, David > (define_insn "copysign3_fcpsgn" > [(set (match_operand:SFDF 0 "gpc_reg_operand" "=3Dd,wa") > - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa") > - (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")] > - UNSPEC_COPYSIGN))] > + (copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa") > + (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))] > "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (mode))" > "@ > fcpsgn %0,%2,%1 > @@ -14984,10 +14982,9 @@ (define_expand "copysign3" > > (define_insn "copysign3_hard" > [(set (match_operand:IEEE128 0 "altivec_register_operand" "=3Dv") > - (unspec:IEEE128 > - [(match_operand:IEEE128 1 "altivec_register_operand" "v") > - (match_operand:IEEE128 2 "altivec_register_operand" "v")] > - UNSPEC_COPYSIGN))] > + (copysign:IEEE128 > + (match_operand:IEEE128 1 "altivec_register_operand" "v") > + (match_operand:IEEE128 2 "altivec_register_operand" "v")))] > "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" > "xscpsgnqp %0,%2,%1" > [(set_attr "type" "vecmove") > @@ -14995,10 +14992,9 @@ (define_insn "copysign3_hard" > > (define_insn "copysign3_soft" > [(set (match_operand:IEEE128 0 "altivec_register_operand" "=3Dv") > - (unspec:IEEE128 > - [(match_operand:IEEE128 1 "altivec_register_operand" "v") > - (match_operand:IEEE128 2 "altivec_register_operand" "v")] > - UNSPEC_COPYSIGN)) > + (copysign:IEEE128 > + (match_operand:IEEE128 1 "altivec_register_operand" "v") > + (match_operand:IEEE128 2 "altivec_register_operand" "v"))) > (clobber (match_scratch:IEEE128 3 "=3D&v"))] > "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" > "xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1" > diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md > index 1ae04c8e0a8..f4fc620b653 100644 > --- a/gcc/config/rs6000/vector.md > +++ b/gcc/config/rs6000/vector.md > @@ -332,8 +332,8 @@ (define_expand "vector_btrunc2" > > (define_expand "vector_copysign3" > [(set (match_operand:VEC_F 0 "vfloat_operand") > - (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand") > - (match_operand:VEC_F 2 "vfloat_operand")] > UNSPEC_COPYSIGN))] > + (copysign:VEC_F (match_operand:VEC_F 1 "vfloat_operand") > + (match_operand:VEC_F 2 "vfloat_operand")))] > "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" > { > if (mode =3D=3D V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode)) > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md > index 4de41e78d51..f3b40229094 100644 > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -2233,10 +2233,9 @@ (define_insn "*vsx_ge__p" > ;; Copy sign > (define_insn "vsx_copysign3" > [(set (match_operand:VSX_F 0 "vsx_register_operand" "=3Dwa") > - (unspec:VSX_F > - [(match_operand:VSX_F 1 "vsx_register_operand" "wa") > - (match_operand:VSX_F 2 "vsx_register_operand" "wa")] > - UNSPEC_COPYSIGN))] > + (copysign:VSX_F > + (match_operand:VSX_F 1 "vsx_register_operand" "wa") > + (match_operand:VSX_F 2 "vsx_register_operand" "wa")))] > "VECTOR_UNIT_VSX_P (mode)" > "xvcpsgnp %x0,%x2,%x1" > [(set_attr "type" "")]) > -- > 2.41.0 > > > -- > Michael Meissner, IBM > PO Box 98, Ayer, Massachusetts, USA, 01432 > email: meissner@linux.ibm.com > --00000000000039ea0a060684a7a9--