[PATCH 0/9] rs6000: SPE removal, part 2

[PATCH 0/9] rs6000: SPE removal, part 2

[Segher Boessenkool]

This patch series makes further updates to remove SPE from the rs6000
port.  The only thing that should be left now is the documentation.

Tested on powerpc64-linux {-m32,-m64}; I'll test on some more systems and
commit later today.


Segher


 gcc/config/rs6000/eabispe.h        | 26 ----------
 gcc/config/rs6000/rs6000-modes.def | 15 ++++--
 gcc/config/rs6000/rs6000-opts.h    |  1 -
 gcc/config/rs6000/rs6000.c         | 97 +++++++++++++-------------------------
 gcc/config/rs6000/rs6000.h         | 12 +----
 gcc/config/rs6000/t-linux          |  4 --
 gcc/config/rs6000/t-rtems          |  6 +--
 gcc/config/rs6000/t-spe            | 72 ----------------------------
 gcc/config/rs6000/vxworks.h        |  8 +---
 gcc/config/rs6000/vxworksae.h      |  4 --
 gcc/config/rs6000/vxworksmils.h    |  4 --
 11 files changed, 48 insertions(+), 201 deletions(-)
 delete mode 100644 gcc/config/rs6000/eabispe.h
 delete mode 100644 gcc/config/rs6000/t-spe

-- 
1.9.3

[PATCH 3/9] rs6000: Remove t-spe

[Segher Boessenkool]

2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/t-spe: Delete file.

---
 gcc/config/rs6000/t-spe | 72 -------------------------------------------------
 1 file changed, 72 deletions(-)
 delete mode 100644 gcc/config/rs6000/t-spe

diff --git a/gcc/config/rs6000/t-spe b/gcc/config/rs6000/t-spe
deleted file mode 100644
index fe5de53..0000000
--- a/gcc/config/rs6000/t-spe
+++ /dev/null
@@ -1,72 +0,0 @@
-# Multilibs for e500
-#
-# Copyright (C) 2003-2017 Free Software Foundation, Inc.
-#
-# This file is part of GCC.
-#
-# GCC is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3, or (at your option)
-# any later version.
-#
-# GCC is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with GCC; see the file COPYING3.  If not see
-# <http://www.gnu.org/licenses/>.
-
-# What we really want are these variants:
-#	-mcpu=7400
-#	-mcpu=7400 -maltivec -mabi=altivec
-#	-mcpu=7400 -msoft-float
-#	-msoft-float
-#	-mno-spe -mabi=no-spe
-#	-mno-spe -mabi=no-spe -mno-isel
-# so we'll need to create exceptions later below.
-
-MULTILIB_OPTIONS	= mcpu=7400 \
-			  maltivec \
-			  mabi=altivec \
-			  msoft-float \
-			  mno-spe \
-			  mabi=no-spe \
-			  mno-isel \
-			  mlittle
-
-MULTILIB_DIRNAMES	= mpc7400 altivec abi-altivec \
-			  nof no-spe no-abi-spe no-isel le
-
-MULTILIB_EXCEPTIONS	= maltivec mabi=altivec mno-spe mabi=no-spe mno-isel \
-			  maltivec/mabi=altivec \
-			  mcpu=7400/maltivec \
-			  mcpu=7400/mabi=altivec \
-			  *mcpu=7400/*mno-spe* \
-			  *mcpu=7400/*mabi=no-spe* \
-			  *mcpu=7400/*mno-isel* \
-			  *maltivec/*msoft-float* \
-			  *maltivec/*mno-spe* \
-			  *maltivec/*mabi=no-spe* \
-			  *maltivec/*mno-isel* \
-			  *mabi=altivec/*msoft-float* \
-			  *mabi=altivec/*mno-spe* \
-			  *mabi=altivec/*mabi=no-spe* \
-			  *mabi=altivec/*mno-isel* \
-			  *msoft-float/*mno-spe* \
-			  *msoft-float/*mabi=no-spe* \
-			  *msoft-float/*mno-isel* \
-			  mno-spe/mno-isel \
-			  mabi=no-spe/mno-isel \
-			  mno-isel/mlittle \
-			  mabi=no-spe/mno-isel/mlittle \
-			  mno-spe/mlittle \
-			  mabi=spe/mlittle \
-			  mcpu=7400/mabi=altivec/mlittle \
-			  mcpu=7400/maltivec/mlittle \
-			  mabi=no-spe/mlittle \
-			  mno-spe/mno-isel/mlittle \
-			  mabi=altivec/mlittle \
-			  maltivec/mlittle \
-			  maltivec/mabi=altivec/mlittle
-- 
1.9.3

[PATCH 4/9] rs6000: Remove eabispe.h

[Segher Boessenkool]

2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/eabispe.h: Delete file.

---
 gcc/config/rs6000/eabispe.h | 26 --------------------------
 1 file changed, 26 deletions(-)
 delete mode 100644 gcc/config/rs6000/eabispe.h

diff --git a/gcc/config/rs6000/eabispe.h b/gcc/config/rs6000/eabispe.h
deleted file mode 100644
index db8030a..0000000
--- a/gcc/config/rs6000/eabispe.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Core target definitions for GNU compiler
-   for PowerPC embedded targeted systems with SPE support.
-   Copyright (C) 2002-2017 Free Software Foundation, Inc.
-   Contributed by Aldy Hernandez (aldyh@redhat.com).
-
-   This file is part of GCC.
-
-   GCC is free software; you can redistribute it and/or modify it
-   under the terms of the GNU General Public License as published
-   by the Free Software Foundation; either version 3, or (at your
-   option) any later version.
-
-   GCC is distributed in the hope that it will be useful, but WITHOUT
-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-   License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GCC; see the file COPYING3.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#undef  TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_STRICT_ALIGN | MASK_EABI)
-
-#undef  ASM_DEFAULT_SPEC
-#define	ASM_DEFAULT_SPEC "-mppc -mspe -me500"
-- 
1.9.3

[PATCH 1/9] rs6000: Sanitize vector modes

[Segher Boessenkool]

This removes the vector modes that were only used by SPE.  It also
rearranges things so it is easier to see what is there, and for what.


2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000-modes.def: Remove all 8-byte vector modes
	except V2SF and V2SI.  Rearrange the vector modes, and add comments.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Remove V8QImode
	and V4HImode.
	(reg_offset_addressing_ok_p): Remove V4HImode and V1DImode.
	(rs6000_legitimate_offset_address_p): Ditto.
	(rs6000_emit_move): Ditto.
	(rs6000_init_builtins): Remove V4HI_type_node.

---
 gcc/config/rs6000/rs6000-modes.def | 15 ++++++++++-----
 gcc/config/rs6000/rs6000.c         | 10 ----------
 2 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def
index fc66fca..65f890e 100644
--- a/gcc/config/rs6000/rs6000-modes.def
+++ b/gcc/config/rs6000/rs6000-modes.def
@@ -41,15 +41,20 @@ CC_MODE (CCFP);
 CC_MODE (CCEQ);
 
 /* Vector modes.  */
-VECTOR_MODES (INT, 8);        /*       V8QI  V4HI V2SI */
+
+/* VMX/VSX.  */
 VECTOR_MODES (INT, 16);       /* V16QI V8HI  V4SI V2DI */
-VECTOR_MODES (INT, 32);       /* V32QI V16HI V8SI V4DI */
-VECTOR_MODE (INT, DI, 1);
-VECTOR_MODE (INT, TI, 1);
-VECTOR_MODES (FLOAT, 8);      /*             V4HF V2SF */
+VECTOR_MODE (INT, TI, 1);     /*                  V1TI */
 VECTOR_MODES (FLOAT, 16);     /*       V8HF  V4SF V2DF */
+
+/* Two VMX/VSX vectors (for permute, select, concat, etc.)  */
+VECTOR_MODES (INT, 32);       /* V32QI V16HI V8SI V4DI */
 VECTOR_MODES (FLOAT, 32);     /*       V16HF V8SF V4DF */
 
+/* Paired single.  */
+VECTOR_MODE (FLOAT, SF, 2);   /* The only valid paired-single mode.  */
+VECTOR_MODE (INT, SI, 2);     /* For paired-single permutes.  */
+
 /* Replacement for TImode that only is allowed in GPRs.  We also use PTImode
    for quad memory atomic operations to force getting an even/odd register
    combination.  */
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 8e82570..b51ffcc 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2450,8 +2450,6 @@ rs6000_debug_reg_global (void)
     SDmode,
     DDmode,
     TDmode,
-    V8QImode,
-    V4HImode,
     V2SImode,
     V16QImode,
     V8HImode,
@@ -8490,9 +8488,7 @@ reg_offset_addressing_ok_p (machine_mode mode)
 	return mode_supports_vsx_dform_quad (mode);
       break;
 
-    case V4HImode:
     case V2SImode:
-    case V1DImode:
     case V2SFmode:
        /* Paired vector modes.  Only reg+reg addressing is valid.  */
       if (TARGET_PAIRED_FLOAT)
@@ -8730,9 +8726,7 @@ rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
   extra = 0;
   switch (mode)
     {
-    case V4HImode:
     case V2SImode:
-    case V1DImode:
     case V2SFmode:
       /* SPE vector modes.  */
       return SPE_CONST_OFFSET_OK (offset);
@@ -10981,10 +10975,8 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
     case V8HImode:
     case V4SFmode:
     case V4SImode:
-    case V4HImode:
     case V2SFmode:
     case V2SImode:
-    case V1DImode:
     case V2DFmode:
     case V2DImode:
     case V1TImode:
@@ -16843,7 +16835,6 @@ rs6000_init_builtins (void)
 				       : "__vector long long",
 				       intDI_type_node, 2);
   V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
-  V4HI_type_node = build_vector_type (intHI_type_node, 4);
   V4SI_type_node = rs6000_vector_type ("__vector signed int",
 				       intSI_type_node, 4);
   V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
@@ -16991,7 +16982,6 @@ rs6000_init_builtins (void)
   builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
   builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
   builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
-  builtin_mode_to_type[V4HImode][0] = V4HI_type_node;
   builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
   builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
   builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
-- 
1.9.3

[PATCH 5/9] rs6000: Updates to t-linux

[Segher Boessenkool]

2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/t-linux: Don't handle SPE.

---
 gcc/config/rs6000/t-linux | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/gcc/config/rs6000/t-linux b/gcc/config/rs6000/t-linux
index 4cb63bd..acfde1f 100644
--- a/gcc/config/rs6000/t-linux
+++ b/gcc/config/rs6000/t-linux
@@ -4,12 +4,8 @@ ifeq (,$(filter $(with_cpu),$(SOFT_FLOAT_CPUS))$(findstring soft,$(with_float)))
 ifneq (,$(findstring powerpc64,$(target)))
 MULTILIB_OSDIRNAMES := .=../lib64$(call if_multiarch,:powerpc64-linux-gnu)
 else
-ifneq (,$(findstring spe,$(target)))
-MULTIARCH_DIRNAME := powerpc-linux-gnuspe$(if $(findstring 8548,$(with_cpu)),,v1)
-else
 MULTIARCH_DIRNAME := powerpc-linux-gnu
 endif
-endif
 ifneq (,$(findstring powerpcle,$(target)))
 MULTIARCH_DIRNAME := $(subst -linux,le-linux,$(MULTIARCH_DIRNAME))
 endif
-- 
1.9.3

[PATCH 6/9] rs6000: Updates to t-rtems

[Segher Boessenkool]

2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/t-rtems: Don't handle SPE.

---
 gcc/config/rs6000/t-rtems | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/t-rtems b/gcc/config/rs6000/t-rtems
index 723c6a3..8290f5c 100644
--- a/gcc/config/rs6000/t-rtems
+++ b/gcc/config/rs6000/t-rtems
@@ -33,8 +33,8 @@ MULTILIB_DIRNAMES += m32
 MULTILIB_OPTIONS += msoft-float
 MULTILIB_DIRNAMES += nof
 
-MULTILIB_OPTIONS += mno-spe/mno-altivec
-MULTILIB_DIRNAMES += nospe noaltivec
+MULTILIB_OPTIONS += mno-altivec
+MULTILIB_DIRNAMES += noaltivec
 
 MULTILIB_MATCHES  	+= ${MULTILIB_MATCHES_ENDIAN}
 MULTILIB_MATCHES	+= ${MULTILIB_MATCHES_SYSV}
@@ -68,7 +68,7 @@ MULTILIB_REQUIRED += mcpu=604/msoft-float
 MULTILIB_REQUIRED += mcpu=7400
 MULTILIB_REQUIRED += mcpu=7400/msoft-float
 MULTILIB_REQUIRED += mcpu=8540
-MULTILIB_REQUIRED += mcpu=8540/msoft-float/mno-spe
+MULTILIB_REQUIRED += mcpu=8540/msoft-float
 MULTILIB_REQUIRED += mcpu=860
 MULTILIB_REQUIRED += mcpu=e6500/m32
 MULTILIB_REQUIRED += mcpu=e6500/m32/msoft-float/mno-altivec
-- 
1.9.3

[PATCH 7/9] rs6000: Remove FIXED_SCRATCH

[Segher Boessenkool]

2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.h (FIXED_SCRATCH): Delete.

---
 gcc/config/rs6000/rs6000.h | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index edfa546..e8305aa 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1330,13 +1330,6 @@ enum data_align { align_abi, align_opt, align_both };
 
 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 
-/* A fixed register used at epilogue generation to address SPE registers
-   with negative offsets.  The 64-bit load/store instructions on the SPE
-   only take positive offsets (and small ones at that), so we need to
-   reserve a register for consing up negative offsets.  */
-
-#define FIXED_SCRATCH 0
-
 /* Specify the registers used for certain standard purposes.
    The values of these macros are register numbers.  */
 
-- 
1.9.3

[PATCH 2/9] rs6000: Remove SPE_CONST_OFFSET_OK

[Segher Boessenkool]

2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.c (SPE_CONST_OFFSET_OK): Delete.
	(rs6000_legitimate_offset_address_p): Return false for anything in
	V2SImode or V2SFmode.

---
 gcc/config/rs6000/rs6000.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index b51ffcc..a1005c0 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -8697,9 +8697,6 @@ legitimate_small_data_p (machine_mode mode, rtx x)
 	  && small_data_operand (x, mode));
 }
 
-/* SPE offset addressing is limited to 5-bits worth of double words.  */
-#define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
-
 bool
 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
 				    bool strict, bool worst_case)
@@ -8728,8 +8725,8 @@ rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
     {
     case V2SImode:
     case V2SFmode:
-      /* SPE vector modes.  */
-      return SPE_CONST_OFFSET_OK (offset);
+      /* Paired single modes: offset addressing isn't valid.  */
+      return false;
 
     case DFmode:
     case DDmode:
-- 
1.9.3

[PATCH 8/9] rs6000: Remove VECTOR_SPE

[Segher Boessenkool]

2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000-opts.h (enum rs6000_vector): Delete VECTOR_SPE.
	* config/rs6000/rs6000.c (rs6000_debug_vector_unit): Delete VECTOR_SPE.

---
 gcc/config/rs6000/rs6000-opts.h | 1 -
 gcc/config/rs6000/rs6000.c      | 1 -
 2 files changed, 2 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 086217a..6dffe8d 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -150,7 +150,6 @@ enum rs6000_vector {
   VECTOR_VSX,			/* Use VSX for vector processing */
   VECTOR_P8_VECTOR,		/* Use ISA 2.07 VSX for vector processing */
   VECTOR_PAIRED,		/* Use paired floating point for vectors */
-  VECTOR_SPE,			/* Use SPE for vector processing */
   VECTOR_OTHER			/* Some other vector unit */
 };
 
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index a1005c0..58ef789 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2236,7 +2236,6 @@ rs6000_debug_vector_unit (enum rs6000_vector v)
     case VECTOR_VSX:	   ret = "vsx";       break;
     case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
     case VECTOR_PAIRED:	   ret = "paired";    break;
-    case VECTOR_SPE:	   ret = "spe";       break;
     case VECTOR_OTHER:	   ret = "other";     break;
     default:		   ret = "unknown";   break;
     }
-- 
1.9.3

[PATCH 9/9] rs6000: Comment fixes + some leftovers

[Segher Boessenkool]

2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.c: Update all comments that mentioned SPE.
	(rs6000_expand_builtin): Remove RS6000_BTC_EVSEL.
	* config/rs6000/rs6000.h (RS6000_BTC_EVSEL): Delete.
	* config/rs6000/vxworks.h (VXCPU_FOR_8548): Delete.  Adjust former use.
	* config/rs6000/vxworksae.h (VXCPU_FOR_8548): Delete.
	* config/rs6000/vxworksmils.h (VXCPU_FOR_8548): Delete.

---
 gcc/config/rs6000/rs6000.c      | 79 ++++++++++++++++-------------------------
 gcc/config/rs6000/rs6000.h      |  5 ++-
 gcc/config/rs6000/vxworks.h     |  8 +----
 gcc/config/rs6000/vxworksae.h   |  4 ---
 gcc/config/rs6000/vxworksmils.h |  4 ---
 5 files changed, 33 insertions(+), 67 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 58ef789..6b28658 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2014,10 +2014,6 @@ rs6000_cpu_name_lookup (const char *name)
    This is ordinarily the length in words of a value of mode MODE
    but can be less for certain modes in special long registers.
 
-   For the SPE, GPRs are 64 bits but only 32 bits are visible in
-   scalar instructions.  The upper 32 bits are only available to the
-   SIMD instructions.
-
    POWER and PowerPC GPRs hold 32 bits worth;
    PowerPC64 GPRs and FPRs point register holds 64 bits worth.  */
 
@@ -2901,9 +2897,7 @@ rs6000_setup_reg_addr_masks (void)
 		addr_mask |= RELOAD_REG_INDEXED;
 
 	      /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
-		 addressing.  Restrict addressing on SPE for 64-bit types
-		 because of the SUBREG hackery used to address 64-bit floats in
-		 '32-bit' GPRs.  If we allow scalars into Altivec registers,
+		 addressing.  If we allow scalars into Altivec registers,
 		 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.  */
 
 	      if (TARGET_UPDATE
@@ -3171,7 +3165,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
       rs6000_vector_align[TImode] = align64;
     }
 
-  /* TODO add SPE and paired floating point vector support.  */
+  /* TODO add paired floating point vector support.  */
 
   /* Register class constraints for the constraints that depend on compile
      switches. When the VSX code was added, different constraints were added
@@ -3827,8 +3821,7 @@ darwin_rs6000_override_options (void)
 
 /* Return the builtin mask of the various options used that could affect which
    builtins were used.  In the past we used target_flags, but we've run out of
-   bits, and some options like SPE and PAIRED are no longer in
-   target_flags.  */
+   bits, and some options like PAIRED are no longer in target_flags.  */
 
 HOST_WIDE_INT
 rs6000_builtin_mask_calculate (void)
@@ -5479,8 +5472,7 @@ rs6000_option_override_internal (bool global_init_p)
 
   /* Set the builtin mask of the various options used that could affect which
      builtins were used.  In the past we used target_flags, but we've run out
-     of bits, and some options like SPE and PAIRED are no longer in
-     target_flags.  */
+     of bits, and some options like PAIRED are no longer in target_flags.  */
   rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
     rs6000_print_builtin_options (stderr, 0, "builtin mask",
@@ -11767,7 +11759,6 @@ function_arg_padding (machine_mode mode, const_tree type)
    However, we're stuck with this because changing the ABI might break
    existing library interfaces.
 
-   Doubleword align SPE vectors.
    Quadword align Altivec/VSX vectors.
    Quadword align large synthetic vector types.   */
 
@@ -12188,18 +12179,17 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
 	  int n_words = rs6000_arg_size (mode, type);
 	  int gregno = cum->sysv_gregno;
 
-	  /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
-	     (r7,r8) or (r9,r10).  As does any other 2 word item such
-	     as complex int due to a historical mistake.  */
+	  /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
+	     As does any other 2 word item such as complex int due to a
+	     historical mistake.  */
 	  if (n_words == 2)
 	    gregno += (1 - gregno) & 1;
 
 	  /* Multi-reg args are not split between registers and stack.  */
 	  if (gregno + n_words - 1 > GP_ARG_MAX_REG)
 	    {
-	      /* Long long and SPE vectors are aligned on the stack.
-		 So are other 2 word items such as complex int due to
-		 a historical mistake.  */
+	      /* Long long is aligned on the stack.  So are other 2 word
+		 items such as complex int due to a historical mistake.  */
 	      if (n_words == 2)
 		cum->words += cum->words & 1;
 	      cum->words += n_words;
@@ -12736,9 +12726,9 @@ rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
 	  int n_words = rs6000_arg_size (mode, type);
 	  int gregno = cum->sysv_gregno;
 
-	  /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
-	     (r7,r8) or (r9,r10).  As does any other 2 word item such
-	     as complex int due to a historical mistake.  */
+	  /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
+	     As does any other 2 word item such as complex int due to a
+	     historical mistake.  */
 	  if (n_words == 2)
 	    gregno += (1 - gregno) & 1;
 
@@ -13675,9 +13665,8 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
       lab_false = create_artificial_label (input_location);
       lab_over = create_artificial_label (input_location);
 
-      /* Long long and SPE vectors are aligned in the registers.
-	 As are any other 2 gpr item such as complex int due to a
-	 historical mistake.  */
+      /* Long long is aligned in the registers.  As are any other 2 gpr
+	 item such as complex int due to a historical mistake.  */
       u = reg;
       if (n_reg == 2 && reg == gpr)
 	{
@@ -16623,7 +16612,6 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
 	case RS6000_BTC_TERNARY:   name3 = "ternary";	break;
 	case RS6000_BTC_PREDICATE: name3 = "predicate";	break;
 	case RS6000_BTC_ABS:	   name3 = "abs";	break;
-	case RS6000_BTC_EVSEL:	   name3 = "evsel";	break;
 	case RS6000_BTC_DST:	   name3 = "dst";	break;
 	}
 
@@ -17011,11 +16999,11 @@ rs6000_init_builtins (void)
   pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
 					     pixel_type_node, 8);
 
-  /* Paired and SPE builtins are only available if you build a compiler with
-     the appropriate options, so only create those builtins with the
-     appropriate compiler option.  Create Altivec and VSX builtins on machines
-     with at least the general purpose extensions (970 and newer) to allow the
-     use of the target attribute.  */
+  /* Paired builtins are only available if you build a compiler with the
+     appropriate options, so only create those builtins with the appropriate
+     compiler option.  Create Altivec and VSX builtins on machines with at
+     least the general purpose extensions (970 and newer) to allow the use of
+     the target attribute.  */
   if (TARGET_PAIRED_FLOAT)
     paired_init_builtins ();
   if (TARGET_EXTRA_BUILTINS)
@@ -18147,11 +18135,11 @@ rs6000_common_init_builtins (void)
       builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
     }
 
-  /* Paired and SPE builtins are only available if you build a compiler with
-     the appropriate options, so only create those builtins with the
-     appropriate compiler option.  Create Altivec and VSX builtins on machines
-     with at least the general purpose extensions (970 and newer) to allow the
-     use of the target attribute..  */
+  /* Paired builtins are only available if you build a compiler with the
+     appropriate options, so only create those builtins with the appropriate
+     compiler option.  Create Altivec and VSX builtins on machines with at
+     least the general purpose extensions (970 and newer) to allow the use of
+     the target attribute..  */
 
   if (TARGET_EXTRA_BUILTINS)
     builtin_mask |= RS6000_BTM_COMMON;
@@ -18395,7 +18383,7 @@ rs6000_common_init_builtins (void)
 	  mode0 = insn_data[icode].operand[0].mode;
 	  if (mode0 == V2SImode)
 	    {
-	      /* code for SPE */
+	      /* code for paired single */
 	      if (! (type = v2si_ftype))
 		{
 		  v2si_ftype
@@ -23109,7 +23097,7 @@ print_operand (FILE *file, rtx x, int code)
 	}
       return;
 
-      /* Print AltiVec or SPE memory operand.  */
+      /* Print AltiVec memory operand.  */
     case 'y':
       {
 	rtx tmp;
@@ -26155,10 +26143,6 @@ rs6000_savres_strategy (rs6000_stack_t *info,
 		+---------------------------------------+
 		| Save area for VRSAVE register (Z)	| 8+P+A+V+L+X+W+Y
 		+---------------------------------------+
-		| SPE: area for 64-bit GP registers	|
-		+---------------------------------------+
-		| SPE alignment padding			|
-		+---------------------------------------+
 		| saved CR (C)				| 8+P+A+V+L+X+W+Y+Z
 		+---------------------------------------+
 		| Save area for GP registers (G)	| 8+P+A+V+L+X+W+Y+Z+C
@@ -29956,7 +29940,6 @@ rs6000_emit_epilogue (int sibcall)
 	  if (regno == INVALID_REGNUM)
 	    break;
 
-	  /* Note: possible use of r0 here to address SPE regs.  */
 	  mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
 				      info->ehrd_offset + frame_off
 				      + reg_size * (int) i);
@@ -36986,7 +36969,7 @@ altivec_expand_vec_perm_const (rtx operands[4])
   return false;
 }
 
-/* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
+/* Expand a Paired Single or VSX Permute Doubleword constant permutation.
    Return true if we match an efficient implementation.  */
 
 static bool
@@ -37213,10 +37196,8 @@ rs6000_parallel_return (machine_mode mode,
 
 /* Target hook for TARGET_FUNCTION_VALUE.
 
-   On the SPE, both FPs and vectors are returned in r3.
-
-   On RS/6000 an integer value is in r3 and a floating-point value is in
-   fp1, unless -msoft-float.  */
+   An integer value is in r3 and a floating-point value is in fp1,
+   unless -msoft-float.  */
 
 static rtx
 rs6000_function_value (const_tree valtype,
@@ -37428,7 +37409,7 @@ rs6000_initial_elimination_offset (int from, int to)
   return offset;
 }
 
-/* Fill in sizes for SPE register high parts in table used by unwinder.  */
+/* Fill in sizes of registers used by unwinder.  */
 
 static void
 rs6000_init_dwarf_reg_sizes_extra (tree address)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index e8305aa..9b73be1 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -698,8 +698,8 @@ extern int rs6000_vector_align[];
 /* For power systems, we want to enable Altivec and VSX builtins even if the
    user did not use -maltivec or -mvsx to allow the builtins to be used inside
    of #pragma GCC target or the target attribute to change the code level for a
-   given system.  The SPE and Paired builtins are only enabled if you configure
-   the compiler for those builtins, and those machines don't support altivec or
+   given system.  The Paired builtins are only enabled if you configure the
+   compiler for those builtins, and those machines don't support altivec or
    VSX.  */
 
 #define TARGET_EXTRA_BUILTINS	(!TARGET_PAIRED_FLOAT			 \
@@ -2553,7 +2553,6 @@ extern int frame_pointer_needed;
 #define RS6000_BTC_TERNARY	0x00000003	/* normal ternary function.  */
 #define RS6000_BTC_PREDICATE	0x00000004	/* predicate function.  */
 #define RS6000_BTC_ABS		0x00000005	/* Altivec/VSX ABS function.  */
-#define RS6000_BTC_EVSEL	0x00000006	/* SPE EVSEL function.  */
 #define RS6000_BTC_DST		0x00000007	/* Altivec DST function.  */
 #define RS6000_BTC_TYPE_MASK	0x0000000f	/* Mask to isolate types */
 
diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h
index ccf6a66..97cc349 100644
--- a/gcc/config/rs6000/vxworks.h
+++ b/gcc/config/rs6000/vxworks.h
@@ -60,12 +60,6 @@ along with GCC; see the file COPYING3.  If not see
 
 #define SUBTARGET_EXTRA_SPECS /* none needed */
 
-/* VxWorks and VxWorksAE (aka 653) expect different CPU values to designate
-   SPE on 8548.  We define a dedicated macro for the base VxWorks here, which
-   the AE configuration will override.  */
-
-#define VXCPU_FOR_8548 "PPC85XX"
-
 /* FIXME: The only reason we allow no -mcpu switch at all is because
    config-ml.in insists on a "." multilib. */
 #define CPP_SPEC \
@@ -79,7 +73,7 @@ along with GCC; see the file COPYING3.  If not see
      mcpu=604 : -DCPU=PPC604  ; \
      mcpu=860 : -DCPU=PPC860  ; \
      mcpu=8540: -DCPU=PPC85XX ; \
-     mcpu=8548: -DCPU=" VXCPU_FOR_8548 "; \
+     mcpu=8548: -DCPU=PPC85XX ; \
               : -DCPU=PPC604  }}" \
 VXWORKS_ADDITIONAL_CPP_SPEC
 
diff --git a/gcc/config/rs6000/vxworksae.h b/gcc/config/rs6000/vxworksae.h
index 27bf470..9f21e91 100644
--- a/gcc/config/rs6000/vxworksae.h
+++ b/gcc/config/rs6000/vxworksae.h
@@ -18,10 +18,6 @@ You should have received a copy of the GNU General Public License
 along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 
-/* VxWorksAE for E500V2 expects a specific CPU value to designate 8548.  */
-#undef VXCPU_FOR_8548
-#define VXCPU_FOR_8548 "PPCE500V2"
-
 /* This platform supports the probing method of stack checking and
    requires 4K of space for executing a possible last chance handler.  */
 #undef STACK_CHECK_PROTECT
diff --git a/gcc/config/rs6000/vxworksmils.h b/gcc/config/rs6000/vxworksmils.h
index 7b1e2cc..a14deb4 100644
--- a/gcc/config/rs6000/vxworksmils.h
+++ b/gcc/config/rs6000/vxworksmils.h
@@ -23,7 +23,3 @@ along with GCC; see the file COPYING3.  If not see
    requires 4K of space for executing a possible last chance handler.  */
 #undef STACK_CHECK_PROTECT
 #define STACK_CHECK_PROTECT 4096
-
-/* VxWorksMILS for E500V2 expects a specific CPU value to designate 8548.  */
-#undef VXCPU_FOR_8548
-#define VXCPU_FOR_8548 "PPC85XX"
-- 
1.9.3

Re: [PATCH 1/9] rs6000: Sanitize vector modes

[David Edelsohn]

On Tue, Jun 13, 2017 at 8:53 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> This removes the vector modes that were only used by SPE.  It also
> rearranges things so it is easier to see what is there, and for what.
>
>
> 2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>
>
>         * config/rs6000/rs6000-modes.def: Remove all 8-byte vector modes
>         except V2SF and V2SI.  Rearrange the vector modes, and add comments.
>         * config/rs6000/rs6000.c (rs6000_debug_reg_global): Remove V8QImode
>         and V4HImode.
>         (reg_offset_addressing_ok_p): Remove V4HImode and V1DImode.
>         (rs6000_legitimate_offset_address_p): Ditto.
>         (rs6000_emit_move): Ditto.
>         (rs6000_init_builtins): Remove V4HI_type_node.

Okay.

Thanks, David

Re: [PATCH 3/9] rs6000: Remove t-spe

[David Edelsohn]

On Tue, Jun 13, 2017 at 8:53 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> 2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>
>
>         * config/rs6000/t-spe: Delete file.

Okay.

Thanks, David

Re: [PATCH 2/9] rs6000: Remove SPE_CONST_OFFSET_OK

[David Edelsohn]

On Tue, Jun 13, 2017 at 8:53 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> 2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>
>
>         * config/rs6000/rs6000.c (SPE_CONST_OFFSET_OK): Delete.
>         (rs6000_legitimate_offset_address_p): Return false for anything in
>         V2SImode or V2SFmode.

Okay.

Thanks, David

Re: [PATCH 4/9] rs6000: Remove eabispe.h

[David Edelsohn]

On Tue, Jun 13, 2017 at 8:53 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> 2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>
>
>         * config/rs6000/eabispe.h: Delete file.

Okay.

Thanks, David

Re: [PATCH 5/9] rs6000: Updates to t-linux

[David Edelsohn]

On Tue, Jun 13, 2017 at 8:53 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> 2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>
>
>         * config/rs6000/t-linux: Don't handle SPE.

Okay.

Thanks, David

Re: [PATCH 6/9] rs6000: Updates to t-rtems

[David Edelsohn]

On Tue, Jun 13, 2017 at 8:53 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> 2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>
>
>         * config/rs6000/t-rtems: Don't handle SPE.

Okay.

Thanks, David

Re: [PATCH 7/9] rs6000: Remove FIXED_SCRATCH

[David Edelsohn]

On Tue, Jun 13, 2017 at 8:53 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> 2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>
>
>         * config/rs6000/rs6000.h (FIXED_SCRATCH): Delete.

Okay.

Thanks, david

Re: [PATCH 8/9] rs6000: Remove VECTOR_SPE

[David Edelsohn]

On Tue, Jun 13, 2017 at 8:53 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> 2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>
>
>         * config/rs6000/rs6000-opts.h (enum rs6000_vector): Delete VECTOR_SPE.
>         * config/rs6000/rs6000.c (rs6000_debug_vector_unit): Delete VECTOR_SPE.

Okay.

Thanks, David

Re: [PATCH 9/9] rs6000: Comment fixes + some leftovers

[David Edelsohn]

On Tue, Jun 13, 2017 at 8:53 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> 2017-06-13  Segher Boessenkool  <segher@kernel.crashing.org>
>
>         * config/rs6000/rs6000.c: Update all comments that mentioned SPE.
>         (rs6000_expand_builtin): Remove RS6000_BTC_EVSEL.
>         * config/rs6000/rs6000.h (RS6000_BTC_EVSEL): Delete.
>         * config/rs6000/vxworks.h (VXCPU_FOR_8548): Delete.  Adjust former use.
>         * config/rs6000/vxworksae.h (VXCPU_FOR_8548): Delete.
>         * config/rs6000/vxworksmils.h (VXCPU_FOR_8548): Delete.

Okay.

Thanks, David