* [RS6000] Tests that use int128_t and -m32
@ 2020-10-25 11:20 Alan Modra
2020-10-25 14:43 ` David Edelsohn
2020-10-26 12:33 ` Segher Boessenkool
0 siblings, 2 replies; 7+ messages in thread
From: Alan Modra @ 2020-10-25 11:20 UTC (permalink / raw)
To: gcc-patches; +Cc: Segher Boessenkool, David Edelsohn
All these tests fail with -m32 due to lack of int128 support, in some
cases with what I thought was not the best error message. For example
vsx_mask-move-runnable.c:34:3: error: unknown type name 'vector'
is misleading. The problem isn't "vector" but "vector __uint128_t".
* gcc.target/powerpc/vsx-load-element-extend-char.c: Require int128.
* gcc.target/powerpc/vsx-load-element-extend-int.c: Likewise.
* gcc.target/powerpc/vsx-load-element-extend-longlong.c: Likewise.
* gcc.target/powerpc/vsx-load-element-extend-short.c: Likewise.
* gcc.target/powerpc/vsx-store-element-truncate-char.c: Likewise.
* gcc.target/powerpc/vsx-store-element-truncate-int.c: Likewise.
* gcc.target/powerpc/vsx-store-element-truncate-longlong.c: Likewise.
* gcc.target/powerpc/vsx-store-element-truncate-short.c: Likewise.
* gcc.target/powerpc/vsx_mask-count-runnable.c: Likewise.
* gcc.target/powerpc/vsx_mask-expand-runnable.c: Likewise.
* gcc.target/powerpc/vsx_mask-extract-runnable.c: Likewise.
* gcc.target/powerpc/vsx_mask-move-runnable.c: Likewise.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
index 0b8cfd610f8..7a7cb77c3a0 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
@@ -4,6 +4,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* { dg-options "-mdejagnu-cpu=power10 -O3" } */
/* At the time of writing, the number of lxvrbx instructions is
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
index b10d3cb43d2..414678c9461 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
@@ -4,6 +4,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* Deliberately set optization to zero for this test to confirm
the lxvr*x instruction is generated. At higher optimization levels
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
index 52fcf2e572f..c1e3ebc25ca 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
@@ -4,6 +4,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* { dg-options "-mdejagnu-cpu=power10 -O3" } */
/* At time of writing, we also geenerate a .constrprop copy
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
index 8fc0cc66eb7..698ba30c6f8 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
@@ -4,6 +4,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* Deliberately set optization to zero for this test to confirm
the lxvr*x instruction is generated. At higher optimization levels
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
index 99f3904983b..53fc2cc9bae 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
@@ -3,6 +3,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* Deliberately set optization to zero for this test to confirm
the stxvr*x instruction is generated. At higher optimization levels
the instruction we are looking for is sometimes replaced by other
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
index 6e2acf83c38..4c64b413e16 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
@@ -3,6 +3,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* Deliberately set optization to zero for this test to confirm
the stxvr*x instruction is generated. At higher optimization levels
the instruction we are looking for is sometimes replaced by other
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
index 7fce6a44d4f..465fbeaf6ab 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
@@ -3,6 +3,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* Deliberately set optization to zero for this test to confirm
the stxvr*x instruction is generated. At higher optimization levels
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
index 17925c87732..f87256921bf 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
@@ -3,6 +3,7 @@
/* { dg-do compile {target power10_ok} } */
/* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
/* Deliberately set optization to zero for this test to confirm
the stxvr*x instruction is generated. At higher optimization levels
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
index 5862517eae9..6ac4ed2173f 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { power10_hw } } } */
/* { dg-do link { target { ! power10_hw } } } */
/* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
/* Check that the expected 128-bit instructions are generated if the processor
supports the 128-bit integer instructions. */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
index 13b4c8afd4f..05fedf77eb9 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { power10_hw } } } */
/* { dg-do link { target { ! power10_hw } } } */
/* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
/* Check that the expected 128-bit instructions are generated if the processor
supports the 128-bit integer instructions. */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
index d58a6b0b682..6e952695905 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { power10_hw } } } */
/* { dg-do link { target { ! power10_hw } } } */
/* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
/* Check that the expected 128-bit instructions are generated if the processor
supports the 128-bit integer instructions. */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
index 9147d67c9d1..c2eb53d3bb2 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { power10_hw } } } */
/* { dg-do link { target { ! power10_hw } } } */
/* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
/* Check that the expected 128-bit instructions are generated if the processor
supports the 128-bit integer instructions. */
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [RS6000] Tests that use int128_t and -m32
2020-10-25 11:20 [RS6000] Tests that use int128_t and -m32 Alan Modra
@ 2020-10-25 14:43 ` David Edelsohn
2020-10-26 12:04 ` Alan Modra
2020-10-26 12:33 ` Segher Boessenkool
1 sibling, 1 reply; 7+ messages in thread
From: David Edelsohn @ 2020-10-25 14:43 UTC (permalink / raw)
To: Alan Modra; +Cc: GCC Patches, Segher Boessenkool
On Sun, Oct 25, 2020 at 7:20 AM Alan Modra <amodra@gmail.com> wrote:
>
> All these tests fail with -m32 due to lack of int128 support, in some
> cases with what I thought was not the best error message. For example
> vsx_mask-move-runnable.c:34:3: error: unknown type name 'vector'
> is misleading. The problem isn't "vector" but "vector __uint128_t".
>
> * gcc.target/powerpc/vsx-load-element-extend-char.c: Require int128.
> * gcc.target/powerpc/vsx-load-element-extend-int.c: Likewise.
> * gcc.target/powerpc/vsx-load-element-extend-longlong.c: Likewise.
> * gcc.target/powerpc/vsx-load-element-extend-short.c: Likewise.
> * gcc.target/powerpc/vsx-store-element-truncate-char.c: Likewise.
> * gcc.target/powerpc/vsx-store-element-truncate-int.c: Likewise.
> * gcc.target/powerpc/vsx-store-element-truncate-longlong.c: Likewise.
> * gcc.target/powerpc/vsx-store-element-truncate-short.c: Likewise.
> * gcc.target/powerpc/vsx_mask-count-runnable.c: Likewise.
> * gcc.target/powerpc/vsx_mask-expand-runnable.c: Likewise.
> * gcc.target/powerpc/vsx_mask-extract-runnable.c: Likewise.
> * gcc.target/powerpc/vsx_mask-move-runnable.c: Likewise.
Good catch.
Another problem with all of the vsx_mask test cases is that they use
-mcpu=power10 instead of -mdejagnu-cpu=power10. Can you follow up
with that fix or do you want me to?
Thanks, David
>
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
> index 0b8cfd610f8..7a7cb77c3a0 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
> @@ -4,6 +4,7 @@
>
> /* { dg-do compile {target power10_ok} } */
> /* { dg-do run {target power10_hw} } */
> +/* { dg-require-effective-target { int128 } } */
> /* { dg-options "-mdejagnu-cpu=power10 -O3" } */
>
> /* At the time of writing, the number of lxvrbx instructions is
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
> index b10d3cb43d2..414678c9461 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
> @@ -4,6 +4,7 @@
>
> /* { dg-do compile {target power10_ok} } */
> /* { dg-do run {target power10_hw} } */
> +/* { dg-require-effective-target { int128 } } */
>
> /* Deliberately set optization to zero for this test to confirm
> the lxvr*x instruction is generated. At higher optimization levels
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
> index 52fcf2e572f..c1e3ebc25ca 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
> @@ -4,6 +4,7 @@
>
> /* { dg-do compile {target power10_ok} } */
> /* { dg-do run {target power10_hw} } */
> +/* { dg-require-effective-target { int128 } } */
> /* { dg-options "-mdejagnu-cpu=power10 -O3" } */
>
> /* At time of writing, we also geenerate a .constrprop copy
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
> index 8fc0cc66eb7..698ba30c6f8 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
> @@ -4,6 +4,7 @@
>
> /* { dg-do compile {target power10_ok} } */
> /* { dg-do run {target power10_hw} } */
> +/* { dg-require-effective-target { int128 } } */
>
> /* Deliberately set optization to zero for this test to confirm
> the lxvr*x instruction is generated. At higher optimization levels
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
> index 99f3904983b..53fc2cc9bae 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
> @@ -3,6 +3,7 @@
>
> /* { dg-do compile {target power10_ok} } */
> /* { dg-do run {target power10_hw} } */
> +/* { dg-require-effective-target { int128 } } */
> /* Deliberately set optization to zero for this test to confirm
> the stxvr*x instruction is generated. At higher optimization levels
> the instruction we are looking for is sometimes replaced by other
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
> index 6e2acf83c38..4c64b413e16 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
> @@ -3,6 +3,7 @@
>
> /* { dg-do compile {target power10_ok} } */
> /* { dg-do run {target power10_hw} } */
> +/* { dg-require-effective-target { int128 } } */
> /* Deliberately set optization to zero for this test to confirm
> the stxvr*x instruction is generated. At higher optimization levels
> the instruction we are looking for is sometimes replaced by other
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
> index 7fce6a44d4f..465fbeaf6ab 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
> @@ -3,6 +3,7 @@
>
> /* { dg-do compile {target power10_ok} } */
> /* { dg-do run {target power10_hw} } */
> +/* { dg-require-effective-target { int128 } } */
>
> /* Deliberately set optization to zero for this test to confirm
> the stxvr*x instruction is generated. At higher optimization levels
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
> index 17925c87732..f87256921bf 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
> @@ -3,6 +3,7 @@
>
> /* { dg-do compile {target power10_ok} } */
> /* { dg-do run {target power10_hw} } */
> +/* { dg-require-effective-target { int128 } } */
>
> /* Deliberately set optization to zero for this test to confirm
> the stxvr*x instruction is generated. At higher optimization levels
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
> index 5862517eae9..6ac4ed2173f 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
> @@ -1,7 +1,7 @@
> /* { dg-do run { target { power10_hw } } } */
> /* { dg-do link { target { ! power10_hw } } } */
> /* { dg-options "-mcpu=power10 -O2" } */
> -/* { dg-require-effective-target power10_ok } */
> +/* { dg-require-effective-target { int128 && power10_ok } } */
>
> /* Check that the expected 128-bit instructions are generated if the processor
> supports the 128-bit integer instructions. */
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
> index 13b4c8afd4f..05fedf77eb9 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
> @@ -1,7 +1,7 @@
> /* { dg-do run { target { power10_hw } } } */
> /* { dg-do link { target { ! power10_hw } } } */
> /* { dg-options "-mcpu=power10 -O2" } */
> -/* { dg-require-effective-target power10_ok } */
> +/* { dg-require-effective-target { int128 && power10_ok } } */
>
> /* Check that the expected 128-bit instructions are generated if the processor
> supports the 128-bit integer instructions. */
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
> index d58a6b0b682..6e952695905 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
> @@ -1,7 +1,7 @@
> /* { dg-do run { target { power10_hw } } } */
> /* { dg-do link { target { ! power10_hw } } } */
> /* { dg-options "-mcpu=power10 -O2" } */
> -/* { dg-require-effective-target power10_ok } */
> +/* { dg-require-effective-target { int128 && power10_ok } } */
>
> /* Check that the expected 128-bit instructions are generated if the processor
> supports the 128-bit integer instructions. */
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
> index 9147d67c9d1..c2eb53d3bb2 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
> @@ -1,7 +1,7 @@
> /* { dg-do run { target { power10_hw } } } */
> /* { dg-do link { target { ! power10_hw } } } */
> /* { dg-options "-mcpu=power10 -O2" } */
> -/* { dg-require-effective-target power10_ok } */
> +/* { dg-require-effective-target { int128 && power10_ok } } */
>
> /* Check that the expected 128-bit instructions are generated if the processor
> supports the 128-bit integer instructions. */
>
> --
> Alan Modra
> Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [RS6000] Tests that use int128_t and -m32
2020-10-25 14:43 ` David Edelsohn
@ 2020-10-26 12:04 ` Alan Modra
2020-10-26 12:35 ` Segher Boessenkool
0 siblings, 1 reply; 7+ messages in thread
From: Alan Modra @ 2020-10-26 12:04 UTC (permalink / raw)
To: David Edelsohn; +Cc: GCC Patches, Segher Boessenkool
On Sun, Oct 25, 2020 at 10:43:12AM -0400, David Edelsohn wrote:
> On Sun, Oct 25, 2020 at 7:20 AM Alan Modra <amodra@gmail.com> wrote:
> >
> > All these tests fail with -m32 due to lack of int128 support, in some
> > cases with what I thought was not the best error message. For example
> > vsx_mask-move-runnable.c:34:3: error: unknown type name 'vector'
> > is misleading. The problem isn't "vector" but "vector __uint128_t".
> >
> > * gcc.target/powerpc/vsx-load-element-extend-char.c: Require int128.
> > * gcc.target/powerpc/vsx-load-element-extend-int.c: Likewise.
> > * gcc.target/powerpc/vsx-load-element-extend-longlong.c: Likewise.
> > * gcc.target/powerpc/vsx-load-element-extend-short.c: Likewise.
> > * gcc.target/powerpc/vsx-store-element-truncate-char.c: Likewise.
> > * gcc.target/powerpc/vsx-store-element-truncate-int.c: Likewise.
> > * gcc.target/powerpc/vsx-store-element-truncate-longlong.c: Likewise.
> > * gcc.target/powerpc/vsx-store-element-truncate-short.c: Likewise.
> > * gcc.target/powerpc/vsx_mask-count-runnable.c: Likewise.
> > * gcc.target/powerpc/vsx_mask-expand-runnable.c: Likewise.
> > * gcc.target/powerpc/vsx_mask-extract-runnable.c: Likewise.
> > * gcc.target/powerpc/vsx_mask-move-runnable.c: Likewise.
>
> Good catch.
>
> Another problem with all of the vsx_mask test cases is that they use
> -mcpu=power10 instead of -mdejagnu-cpu=power10. Can you follow up
> with that fix or do you want me to?
Sure, I can do that if you're pre-approving the patch.
gcc.target/powerpc/pr93122.c too.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [RS6000] Tests that use int128_t and -m32
2020-10-25 11:20 [RS6000] Tests that use int128_t and -m32 Alan Modra
2020-10-25 14:43 ` David Edelsohn
@ 2020-10-26 12:33 ` Segher Boessenkool
2020-10-26 23:09 ` Alan Modra
1 sibling, 1 reply; 7+ messages in thread
From: Segher Boessenkool @ 2020-10-26 12:33 UTC (permalink / raw)
To: Alan Modra; +Cc: gcc-patches, David Edelsohn
Hi Alan,
On Sun, Oct 25, 2020 at 09:50:01PM +1030, Alan Modra wrote:
> All these tests fail with -m32 due to lack of int128 support,
Is there any good reason __int128 is not enabled for rs6000 -m32, btw?
> in some
> cases with what I thought was not the best error message. For example
> vsx_mask-move-runnable.c:34:3: error: unknown type name 'vector'
> is misleading. The problem isn't "vector" but "vector __uint128_t".
Ouch, yes. Do you see a simple way to fix that?
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
> index 0b8cfd610f8..7a7cb77c3a0 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
> @@ -4,6 +4,7 @@
>
> /* { dg-do compile {target power10_ok} } */
> /* { dg-do run {target power10_hw} } */
> +/* { dg-require-effective-target { int128 } } */
> /* { dg-options "-mdejagnu-cpu=power10 -O3" } */
You might want to write this as {int128}, to keep the same style as the
other statements. Or leave off the braces completely, they aren't
necessary here, int128 is a single word :-)
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
> index 5862517eae9..6ac4ed2173f 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
> @@ -1,7 +1,7 @@
> /* { dg-do run { target { power10_hw } } } */
> /* { dg-do link { target { ! power10_hw } } } */
> /* { dg-options "-mcpu=power10 -O2" } */
> -/* { dg-require-effective-target power10_ok } */
> +/* { dg-require-effective-target { int128 && power10_ok } } */
Or write it as two require statements, as we do most of the time?
Okay for trunk (with those tweaks if you want). Thanks!
Segher
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [RS6000] Tests that use int128_t and -m32
2020-10-26 12:04 ` Alan Modra
@ 2020-10-26 12:35 ` Segher Boessenkool
0 siblings, 0 replies; 7+ messages in thread
From: Segher Boessenkool @ 2020-10-26 12:35 UTC (permalink / raw)
To: Alan Modra; +Cc: David Edelsohn, GCC Patches
On Mon, Oct 26, 2020 at 10:34:20PM +1030, Alan Modra wrote:
> On Sun, Oct 25, 2020 at 10:43:12AM -0400, David Edelsohn wrote:
> > Another problem with all of the vsx_mask test cases is that they use
> > -mcpu=power10 instead of -mdejagnu-cpu=power10. Can you follow up
> > with that fix or do you want me to?
>
> Sure, I can do that if you're pre-approving the patch.
> gcc.target/powerpc/pr93122.c too.
This is obvious and trivial, doesn't need approval (just send a mail
what you did). Thanks :-)
Segher
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [RS6000] Tests that use int128_t and -m32
2020-10-26 12:33 ` Segher Boessenkool
@ 2020-10-26 23:09 ` Alan Modra
2020-10-27 0:57 ` [RS6000] Separate dg-require-effective-target options Alan Modra
0 siblings, 1 reply; 7+ messages in thread
From: Alan Modra @ 2020-10-26 23:09 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: gcc-patches, David Edelsohn
On Mon, Oct 26, 2020 at 07:33:49AM -0500, Segher Boessenkool wrote:
> On Sun, Oct 25, 2020 at 09:50:01PM +1030, Alan Modra wrote:
> > All these tests fail with -m32 due to lack of int128 support,
>
> Is there any good reason __int128 is not enabled for rs6000 -m32, btw?
Lack of addti3 and subti3 perhaps?
> > in some
> > cases with what I thought was not the best error message. For example
> > vsx_mask-move-runnable.c:34:3: error: unknown type name 'vector'
> > is misleading. The problem isn't "vector" but "vector __uint128_t".
>
> Ouch, yes. Do you see a simple way to fix that?
I haven't looked. The only reason I commented on the error was in the
hope that someone who knows gcc intimately enough to fix this without
much effort would do so. :-)
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 7+ messages in thread
* [RS6000] Separate dg-require-effective-target options
2020-10-26 23:09 ` Alan Modra
@ 2020-10-27 0:57 ` Alan Modra
0 siblings, 0 replies; 7+ messages in thread
From: Alan Modra @ 2020-10-27 0:57 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: gcc-patches, David Edelsohn
Subject was "[RS6000] Tests that use int128_t and -m32"
I meant to make this change before committing too. Pushed.
* gcc.target/powerpc/vsx_mask-count-runnable.c: Separate options
passed to dg-require-effective-target.
* gcc.target/powerpc/vsx_mask-expand-runnable.c: Likewise.
* gcc.target/powerpc/vsx_mask-extract-runnable.c: Likewise.
* gcc.target/powerpc/vsx_mask-move-runnable.c: Likewise.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
index 6aa165c675c..28aa7da9d1f 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
@@ -1,7 +1,8 @@
/* { dg-do run { target { power10_hw } } } */
/* { dg-do link { target { ! power10_hw } } } */
/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-/* { dg-require-effective-target { int128 && power10_ok } } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target int128 } */
/* Check that the expected 128-bit instructions are generated if the processor
supports the 128-bit integer instructions. */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
index 9fdfa4a8b82..68c1c3f1c9a 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
@@ -1,7 +1,8 @@
/* { dg-do run { target { power10_hw } } } */
/* { dg-do link { target { ! power10_hw } } } */
/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-/* { dg-require-effective-target { int128 && power10_ok } } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target int128 } */
/* Check that the expected 128-bit instructions are generated if the processor
supports the 128-bit integer instructions. */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
index a038e56c9cd..4664807a69e 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
@@ -1,7 +1,8 @@
/* { dg-do run { target { power10_hw } } } */
/* { dg-do link { target { ! power10_hw } } } */
/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-/* { dg-require-effective-target { int128 && power10_ok } } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target int128 } */
/* Check that the expected 128-bit instructions are generated if the processor
supports the 128-bit integer instructions. */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
index 6f87e60ea41..58954dc5fc9 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
@@ -1,7 +1,8 @@
/* { dg-do run { target { power10_hw } } } */
/* { dg-do link { target { ! power10_hw } } } */
/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-/* { dg-require-effective-target { int128 && power10_ok } } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target int128 } */
/* Check that the expected 128-bit instructions are generated if the processor
supports the 128-bit integer instructions. */
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-10-27 0:57 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2020-10-25 11:20 [RS6000] Tests that use int128_t and -m32 Alan Modra
2020-10-25 14:43 ` David Edelsohn
2020-10-26 12:04 ` Alan Modra
2020-10-26 12:35 ` Segher Boessenkool
2020-10-26 12:33 ` Segher Boessenkool
2020-10-26 23:09 ` Alan Modra
2020-10-27 0:57 ` [RS6000] Separate dg-require-effective-target options Alan Modra
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