From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by sourceware.org (Postfix) with ESMTPS id D28603858401; Thu, 5 Oct 2023 16:54:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D28603858401 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-9adb9fa7200so279764066b.0; Thu, 05 Oct 2023 09:54:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696524863; x=1697129663; darn=gcc.gnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=bWT3Xro+TSPO+1LluUlwCmzEWnvLJ1+ZPyPkQUyF3Jw=; b=gzfprz7wrklxBqm4ZYi2rIeltUvgBO7RAS2UcTiAQSw6eLcVWc5MnJ0DFHxP3JVrSA NkhuYLDBAf+UfxOZPddp1dUVM44LRIyf26sdxdhrEYNYOp2C7ocM2nMPR3csLSAubTNA yxJQU0yBRVBhDcoDf5LiBm/oUSMQSDar25bNelubhvYLgqwYGleM7I9JFUA4oCeWY0qN kjzqg7i4voq8Zw89CrZIp8knfRZAyUYDEhA8DDaijLXArl++blEMr8Ly/fyjMD1K3Qug aKpnkFYudf01ItlW9zqX6E/GK8y6YXiLeJCZ/vuJVSOJ2JzUCM4N2MXn/6UpeHBXi9pk ktwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696524863; x=1697129663; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=bWT3Xro+TSPO+1LluUlwCmzEWnvLJ1+ZPyPkQUyF3Jw=; b=jXXVeh4TvVOVy3StGgB3uE+luB9Pdzj9tKzl8ycOshTmj6LYzdK/JRZE1wgufS2mnw kUl1ufKPb4FQ28Q2BdcFp3hGs20QizbUuL3xMGE6lGrJ2VEQI0iXUeJhc8Cx0/Nde5uo aReL7LfsMtDANv9B9zSD844waZuxnK4mbKsQuhsC6RrtoD5L0nnHhLABS4yfXKtnP7Di JwLUcYXZ17IPSWERTlGtCO5D4M8cIaUw9vmXsoTFl0M8pE8vCjOVBkede5uNTQxXHsZb Z0wyYNY8vXkDghnfkhf1Qv8GlftFgwTE8WxFS6hol/5lYIRApyn5Q4B+1V4+NkKs2nEB HgVQ== X-Gm-Message-State: AOJu0YyJm6cqxaV7MfFx9OFCUj96/A4F0VVUYNVvwdKpbwKAeDBrGcYV 7Ts3m1z0kQNgxadHy24hBltx70yMWsDIDaSnh54= X-Google-Smtp-Source: AGHT+IHn2MIBu/EsGwVAsTNg7knmRoqJDrDUny0oOV+GcHwupuhQGth3fRdmBiqkYb85lU8mc3L0ZyLKGs3FSNIDVe4= X-Received: by 2002:a17:907:6d27:b0:9a5:7d34:e68a with SMTP id sa39-20020a1709076d2700b009a57d34e68amr1580427ejc.28.1696524863270; Thu, 05 Oct 2023 09:54:23 -0700 (PDT) MIME-Version: 1.0 References: <20231005041346.3625108-1-guojiufu@linux.ibm.com> <20231005041346.3625108-2-guojiufu@linux.ibm.com> In-Reply-To: <20231005041346.3625108-2-guojiufu@linux.ibm.com> From: David Edelsohn Date: Thu, 5 Oct 2023 12:54:12 -0400 Message-ID: Subject: Re: [PATCH V5 2/2] rs6000: use mtvsrws to move sf from si p9 To: Jiufu Guo Cc: gcc-patches@gcc.gnu.org, segher@kernel.crashing.org, linkw@gcc.gnu.org, bergner@linux.ibm.com Content-Type: multipart/alternative; boundary="000000000000d3f5200606faf9a8" X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000d3f5200606faf9a8 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Oct 5, 2023 at 12:14=E2=80=AFAM Jiufu Guo = wrote: > Hi, > > As mentioned in PR108338, on p9, we could use mtvsrws to implement > the bitcast from SI to SF (or lowpart DI to SF). > > For example: > *(long long*)buff =3D di; > float f =3D *(float*)(buff); > > "sldi 9,3,32 ; mtvsrd 1,9 ; xscvspdpn 1,1" is generated. > A better one would be "mtvsrws 1,3 ; xscvspdpn 1,1". > > Compare with previous patch: > https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628791.html > According to review comments, this version refines commit message > and words in comments, also updates the test case > > Pass bootstrap and regtest on ppc64{,le}. > Is this ok for trunk? > Okay. Thanks, David > > BR, > Jeff (Jiufu Guo) > > PR target/108338 > > gcc/ChangeLog: > > * config/rs6000/rs6000.md (movsf_from_si): Update to generate > mtvsrws > for P9. > > gcc/testsuite/ChangeLog: > > * gcc.target/powerpc/pr108338.c: Updated to check mtvsrws for p9. > > --- > gcc/config/rs6000/rs6000.md | 25 ++++++++++++++++----- > gcc/testsuite/gcc.target/powerpc/pr108338.c | 21 ++++++++++++++--- > 2 files changed, 37 insertions(+), 9 deletions(-) > > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md > index 56bd8bc1147..d6dfb25cea0 100644 > --- a/gcc/config/rs6000/rs6000.md > +++ b/gcc/config/rs6000/rs6000.md > @@ -8283,13 +8283,26 @@ (define_insn_and_split "movsf_from_si" > { > rtx op0 =3D operands[0]; > rtx op1 =3D operands[1]; > - rtx op2 =3D operands[2]; > - rtx op1_di =3D gen_rtx_REG (DImode, REGNO (op1)); > > - /* Move SF value to upper 32-bits for xscvspdpn. */ > - emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32))); > - emit_insn (gen_p8_mtvsrd_sf (op0, op2)); > - emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); > + /* Move lowpart 32-bits from register for SFmode. */ > + if (TARGET_P9_VECTOR) > + { > + /* Using mtvsrws;xscvspdpn. */ > + rtx op0_v =3D gen_rtx_REG (V4SImode, REGNO (op0)); > + emit_insn (gen_vsx_splat_v4si (op0_v, op1)); > + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); > + } > + else > + { > + rtx op2 =3D operands[2]; > + rtx op1_di =3D gen_rtx_REG (DImode, REGNO (op1)); > + > + /* Using sldi;mtvsrd;xscvspdpn. */ > + emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32))); > + emit_insn (gen_p8_mtvsrd_sf (op0, op2)); > + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); > + } > + > DONE; > } > [(set_attr "length" > diff --git a/gcc/testsuite/gcc.target/powerpc/pr108338.c > b/gcc/testsuite/gcc.target/powerpc/pr108338.c > index bd83c0b3ad8..5f2f62866ee 100644 > --- a/gcc/testsuite/gcc.target/powerpc/pr108338.c > +++ b/gcc/testsuite/gcc.target/powerpc/pr108338.c > @@ -3,9 +3,12 @@ > /* { dg-options "-O2 -save-temps" } */ > > /* Under lp64, parameter 'v' is in DI regs, then bitcast sub DI to SF. */ > -/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 1 { target { lp64 && > has_arch_pwr8 } } } } */ > -/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 && > has_arch_pwr8 } } } } */ > +/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 2 { target { lp64 && > has_arch_pwr8 } } } } */ > +/* { dg-final { scan-assembler-times {\mmtvsrd\M} 2 { target { lp64 && { > has_arch_pwr8 && { ! has_arch_pwr9 } } } } } } */ > +/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 && > has_arch_pwr9 } } } } */ > +/* { dg-final { scan-assembler-times {\mmtvsrws\M} 1 { target { lp64 && > has_arch_pwr9 } } } } */ > /* { dg-final { scan-assembler-times {\mrldicr\M} 1 { target { lp64 && > has_arch_pwr8 } } } } */ > +/* { dg-final { scan-assembler-times {\msldi\M} 1 { target { lp64 && { > has_arch_pwr8 && { ! has_arch_pwr9 } } } } } } */ > > struct di_sf_sf > { > @@ -22,16 +25,28 @@ sf_from_high32bit_di (struct di_sf_sf v) > #endif > } > > +float __attribute__ ((noipa)) > +sf_from_low32bit_di (struct di_sf_sf v) > +{ > +#ifdef __LITTLE_ENDIAN__ > + return v.f1; > +#else > + return v.f2; > +#endif > +} > + > int main() > { > struct di_sf_sf v; > v.f1 =3D v.f2 =3D 0.0f; > #ifdef __LITTLE_ENDIAN__ > + v.f1 =3D 1.0f; > v.f2 =3D 2.0f; > #else > v.f1 =3D 2.0f; > + v.f2 =3D 1.0f; > #endif > - if (sf_from_high32bit_di (v) !=3D 2.0f) > + if (sf_from_high32bit_di (v) !=3D 2.0f || sf_from_low32bit_di (v) !=3D= 1.0f) > __builtin_abort (); > return 0; > } > -- > 2.25.1 > > --000000000000d3f5200606faf9a8--