From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x931.google.com (mail-ua1-x931.google.com [IPv6:2607:f8b0:4864:20::931]) by sourceware.org (Postfix) with ESMTPS id AE2CB3858410 for ; Tue, 14 Dec 2021 16:57:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org AE2CB3858410 Received: by mail-ua1-x931.google.com with SMTP id 30so35927325uag.13 for ; Tue, 14 Dec 2021 08:57:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=r4jL4znxDxHMlmlltxvdIy/dE2uhOK+8MFtV3OuYDN8=; b=vZOVKDGrAea9B7LfvyPYqLQsZXjB9oBjW78Jp3sgE8OblN3nncR+T3VjMb5YctThJR /wXUQTvFYnysMEqojLe/KUmM51D3R2MJtfLQlLlon9H1oxlKub2w7iWj863jo7dlt1hB ianaq22MrYvdZYeHyvsIowLX82ooVRyNN/qp0KQa69ctvM6am80fZnUq7tl335l7AKFP pViJvo9kqM2VtBSQMJnQsGMinwe6DhHxyUdFhfaX3tv3Sr7iIlV94rPs7sVNqwwD4d+w KJ4yvJ9SZACiiBJwm3yejB6MxKbJmB/pfqWODV2A91DIiWAiMwJD2qPIuoHEt8Q6y+sT OBwA== X-Gm-Message-State: AOAM531GtVyDv21jzwtjIuxtPtZgGBNnL/h4/pDkNR5I5ZskSEFbd0b/ ZUbwbsEGN39Zbqffdtiz/23KXouHA/qMQE+6trI= X-Google-Smtp-Source: ABdhPJxPaXJwySdzt7Za63gTgSaV1+2PD6plOlbgVQTwOTAsP11IHzwJiJf8NXQjv8svTbHTSvNYpcp5gVwTgqUB+fE= X-Received: by 2002:a67:cb0d:: with SMTP id b13mr17004vsl.81.1639501036209; Tue, 14 Dec 2021 08:57:16 -0800 (PST) MIME-Version: 1.0 References: <4d3c58e8e5f0361f807be7ad9b36158227b5c0d2.camel@vnet.ibm.com> In-Reply-To: From: David Edelsohn Date: Tue, 14 Dec 2021 11:57:05 -0500 Message-ID: Subject: Re: [PATCH 2/5] Add Power10 XXSPLTI* and LXVKQ instructions (LXVKQ) To: Michael Meissner , Segher Boessenkool Cc: GCC Patches , will schmidt , Bill Schmidt , Peter Bergner Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Dec 2021 16:57:18 -0000 On Fri, Nov 5, 2021 at 2:01 PM Michael Meissner wrote: > > On Fri, Nov 05, 2021 at 12:52:51PM -0500, will schmidt wrote: > > > diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md > > > index 956e42bc514..e0d1c718e9f 100644 > > > --- a/gcc/config/rs6000/predicates.md > > > +++ b/gcc/config/rs6000/predicates.md > > > @@ -601,6 +601,14 @@ (define_predicate "easy_fp_constant" > > > if (TARGET_VSX && op == CONST0_RTX (mode)) > > > return 1; > > > > > > + /* Constants that can be generated with ISA 3.1 instructions are easy. */ > > > > Easy is relative, but OK. > > The names of the function is easy_fp_constant. > > > > + vec_const_128bit_type vsx_const; > > > + if (TARGET_POWER10 && vec_const_128bit_to_bytes (op, mode, &vsx_const)) > > > + { > > > + if (constant_generates_lxvkq (&vsx_const) != 0) > > > + return true; > > > + } > > > + > > > /* Otherwise consider floating point constants hard, so that the > > > constant gets pushed to memory during the early RTL phases. This > > > has the advantage that double precision constants that can be > > > @@ -609,6 +617,23 @@ (define_predicate "easy_fp_constant" > > > return 0; > > > }) > > > > > > +;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded > > > +;; via the LXVKQ instruction. > > > + > > > +(define_predicate "easy_vector_constant_ieee128" > > > + (match_code "const_vector,const_double") > > > +{ > > > + vec_const_128bit_type vsx_const; > > > + > > > + /* Can we generate the LXVKQ instruction? */ > > > + if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10 > > > + || !TARGET_VSX) > > > + return false; > > > > Presumably all of the checks there are valid. (Can we have power10 > > without float128_hw or ieee128_constant flags set?) I do notice the > > addition of an ieee128_constant flag below. > > Yes, we can have power10 without float128_hw. At the moment, 32-bit big endian > does not enable the 128-bit IEEE instructions. Also when we are building the > bits in libgcc that can switch between compiling the software routines and the > routines used for IEEE hardware, and when we are building the IEEE 128-bit > software emulation functions we need to explicitly turn off IEEE 128-bit > hardware support. > > Similarly for VSX, if the user explicitly says -mno-vsx, then we can't enable > this instruction. > > > Ok. I did look at this a bit before it clicked, so would suggest a > > comment stl "All of the constants that can be loaded by lxvkq will have > > zero in the bottom 3 words, so ensure those are zero before we use a > > switch based on the nonzero portion of the constant." > > > > It would be fine as-is too. :-) > > Ok. Okay. Thanks, David