From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26426 invoked by alias); 10 Jun 2013 15:41:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 26394 invoked by uid 89); 10 Jun 2013 15:41:23 -0000 X-Spam-SWARE-Status: No, score=-3.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,KHOP_THREADED,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE,SPF_PASS autolearn=ham version=3.3.1 Received: from mail-ve0-f174.google.com (HELO mail-ve0-f174.google.com) (209.85.128.174) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Mon, 10 Jun 2013 15:41:22 +0000 Received: by mail-ve0-f174.google.com with SMTP id oz10so4925227veb.33 for ; Mon, 10 Jun 2013 08:41:20 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.52.24.237 with SMTP id x13mr5033829vdf.114.1370878880216; Mon, 10 Jun 2013 08:41:20 -0700 (PDT) Received: by 10.220.118.135 with HTTP; Mon, 10 Jun 2013 08:41:20 -0700 (PDT) In-Reply-To: <20130529203207.GA24280@ibm-tiger.the-meissners.org> References: <20130520204053.GA21090@ibm-tiger.the-meissners.org> <20130522142533.GA25178@ibm-tiger.the-meissners.org> <20130529203207.GA24280@ibm-tiger.the-meissners.org> Date: Mon, 10 Jun 2013 15:41:00 -0000 Message-ID: Subject: Re: [PATCH, rs6000] power8 patches, patch #6, direct move & basic quad load/store From: David Edelsohn To: Michael Meissner , GCC Patches , Pat Haugen , Peter Bergner Content-Type: text/plain; charset=ISO-8859-1 X-SW-Source: 2013-06/txt/msg00511.txt.bz2 Mike, This patch is okay, but something seems really broken with respect to TImode. I don't know if we have to separate TImode from V1TImode or some distinction for atomics from other uses of TImode. This isn't like float modes where they mostly live in FPRs and only occassionally need to live in GPRs. TImode between VSX and GPRs really is bimodal. Something is wrong with this preferencing design. Maybe we need a separate set of logical TImode instructions for the atomic ops with a neutral set of preferences on the constraints for movti. Then the registers chosen for the computation will correctly drive the register allocation decisions. Thanks, David