[PATCH 0/3] rs6000: Some updates for rotate etc.

[PATCH 0/3] rs6000: Some updates for rotate etc.

[Segher Boessenkool]

Hi all,

Two updates for the rotate revamp, and a third patch that won't apply
without it.  I'll fold the first two together with the big patch, if
approved.

Everything bootstrapped and tested on powerpc64-linux, as usual; no
regressions.


Segher


Segher Boessenkool (3):
  Doc fixes for rot
  Fix shift amount (GPR->SI)
  lt0_disi

 gcc/config/rs6000/constraints.md |  2 +-
 gcc/config/rs6000/rs6000.md      | 35 +++++++++++++++++++++++------------
 gcc/doc/md.texi                  | 12 ------------
 3 files changed, 24 insertions(+), 25 deletions(-)

-- 
1.8.1.4

[PATCH 1/3] Doc fixes for rot

[Segher Boessenkool]

This removes the removed constraints from the documentation.  It also
removes "q" (for MQ) which hasn't existed for a while.


2015-07-20  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/constraints.md: Update "available letters" comment.
	* doc/md.texi (Machine Constraints): Remove q, S, T, t constraints.

---
 gcc/config/rs6000/constraints.md |  2 +-
 gcc/doc/md.texi                  | 12 ------------
 2 files changed, 1 insertion(+), 13 deletions(-)

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index d70b817..893a826 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -17,7 +17,7 @@
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 
-;; Available constraint letters: "e", "k", "q", "u", "A", "B", "C", "D"
+;; Available constraint letters: e k q t u A B C D S T
 
 ;; Register constraints
 
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 4fba7acc..0ec229f 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3173,9 +3173,6 @@ instructions.
 @item h
 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
 
-@item q
-@samp{MQ} register
-
 @item c
 @samp{CTR} register
 
@@ -3268,18 +3265,9 @@ AIX TOC entry
 Address operand that is an indexed or indirect from a register (@samp{p} is
 preferable for @code{asm} statements)
 
-@item S
-Constant suitable as a 64-bit mask operand
-
-@item T
-Constant suitable as a 32-bit mask operand
-
 @item U
 System V Release 4 small data area reference
 
-@item t
-AND masks that can be performed by two rldic@{l, r@} instructions
-
 @item W
 Vector constant that does not require memory
 
-- 
1.8.1.4

[PATCH 2/3] Fix shift amount (GPR->SI)

[Segher Boessenkool]

This changes the shift amount to always be SI (as it should be), not GPR.
It doesn't matter for constant shifts, but there are some variable shifts
as well, and consistency is good.

No changelog, I'll fold it into the previous big patch, if approved.


Segher

---
 gcc/config/rs6000/rs6000.md | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d8529f8..5727068 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3039,7 +3039,7 @@ (define_insn_and_split "*and<mode>3_imm_dot_shifted"
 	(compare:CC
 	  (and:GPR
 	    (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
-			  (match_operand:GPR 4 "const_int_operand" "n,n"))
+			  (match_operand:SI 4 "const_int_operand" "n,n"))
 	    (match_operand:GPR 2 "const_int_operand" "n,n"))
 	  (const_int 0)))
    (clobber (match_scratch:GPR 0 "=r,r"))]
@@ -3402,7 +3402,7 @@ (define_insn "*rotl<mode>3_mask"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(and:GPR (match_operator:GPR 4 "rotate_mask_operator"
 		  [(match_operand:GPR 1 "gpc_reg_operand" "r")
-		   (match_operand:GPR 2 "reg_or_cint_operand" "rn")])
+		   (match_operand:SI 2 "reg_or_cint_operand" "rn")])
 		 (match_operand:GPR 3 "const_int_operand" "n")))]
   "rs6000_is_valid_shift_mask (operands[3], operands[4], <MODE>mode)"
 {
@@ -3416,7 +3416,7 @@ (define_insn_and_split "*rotl<mode>3_mask_dot"
 	(compare:CC
 	  (and:GPR (match_operator:GPR 4 "rotate_mask_operator"
 		    [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
-		     (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")])
+		     (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")])
 		   (match_operand:GPR 3 "const_int_operand" "n,n"))
 	  (const_int 0)))
    (clobber (match_scratch:GPR 0 "=r,r"))]
@@ -3447,7 +3447,7 @@ (define_insn_and_split "*rotl<mode>3_mask_dot2"
 	(compare:CC
 	  (and:GPR (match_operator:GPR 4 "rotate_mask_operator"
 		    [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
-		     (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")])
+		     (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")])
 		   (match_operand:GPR 3 "const_int_operand" "n,n"))
 	  (const_int 0)))
    (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
@@ -3482,7 +3482,7 @@ (define_insn "*rotl<mode>3_insert"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(ior:GPR (and:GPR (match_operator:GPR 4 "rotate_mask_operator"
 			   [(match_operand:GPR 1 "gpc_reg_operand" "r")
-			    (match_operand:GPR 2 "const_int_operand" "n")])
+			    (match_operand:SI 2 "const_int_operand" "n")])
 			  (match_operand:GPR 3 "const_int_operand" "n"))
 		 (and:GPR (match_operand:GPR 5 "gpc_reg_operand" "0")
 			  (match_operand:GPR 6 "const_int_operand" "n"))))]
@@ -3502,7 +3502,7 @@ (define_insn "*rotl<mode>3_insert_2"
 			  (match_operand:GPR 6 "const_int_operand" "n"))
 		 (and:GPR (match_operator:GPR 4 "rotate_mask_operator"
 			   [(match_operand:GPR 1 "gpc_reg_operand" "r")
-			    (match_operand:GPR 2 "const_int_operand" "n")])
+			    (match_operand:SI 2 "const_int_operand" "n")])
 			  (match_operand:GPR 3 "const_int_operand" "n"))))]
   "rs6000_is_valid_insert_mask (operands[3], operands[4], <MODE>mode)
    && UINTVAL (operands[3]) + UINTVAL (operands[6]) + 1 == 0"
@@ -3517,7 +3517,7 @@ (define_insn "*rotl<mode>3_insert_3"
 	(ior:GPR (and:GPR (match_operand:GPR 3 "gpc_reg_operand" "0")
 			  (match_operand:GPR 4 "const_int_operand" "n"))
 		 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-			     (match_operand:GPR 2 "const_int_operand" "n"))))]
+			     (match_operand:SI 2 "const_int_operand" "n"))))]
   "INTVAL (operands[2]) == exact_log2 (UINTVAL (operands[4]) + 1)"
 {
   if (<MODE>mode == SImode)
@@ -3532,7 +3532,7 @@ (define_insn "*rotl<mode>3_insert_4"
 	(ior:GPR (and:GPR (match_operand:GPR 3 "gpc_reg_operand" "0")
 			  (match_operand:GPR 4 "const_int_operand" "n"))
 		 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-			       (match_operand:GPR 2 "const_int_operand" "n"))))]
+			       (match_operand:SI 2 "const_int_operand" "n"))))]
   "<MODE>mode == SImode &&
    GET_MODE_PRECISION (<MODE>mode)
    == INTVAL (operands[2]) + exact_log2 (-UINTVAL (operands[4]))"
@@ -3552,9 +3552,9 @@ (define_insn "*rotl<mode>3_insert_4"
 (define_split
   [(set (match_operand:GPR 0 "gpc_reg_operand")
 	(ior:GPR (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand")
-			     (match_operand:GPR 3 "const_int_operand"))
+			     (match_operand:SI 3 "const_int_operand"))
 		 (lshiftrt:GPR (match_operand:GPR 2 "gpc_reg_operand")
-			       (match_operand:GPR 4 "const_int_operand"))))]
+			       (match_operand:SI 4 "const_int_operand"))))]
   "can_create_pseudo_p ()
    && INTVAL (operands[3]) + INTVAL (operands[4])
       >= GET_MODE_PRECISION (<MODE>mode)"
@@ -3576,9 +3576,9 @@ (define_split
 (define_split
   [(set (match_operand:GPR 0 "gpc_reg_operand")
 	(ior:GPR (lshiftrt:GPR (match_operand:GPR 2 "gpc_reg_operand")
-			       (match_operand:GPR 4 "const_int_operand"))
+			       (match_operand:SI 4 "const_int_operand"))
 		 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand")
-			     (match_operand:GPR 3 "const_int_operand"))))]
+			     (match_operand:SI 3 "const_int_operand"))))]
   "can_create_pseudo_p ()
    && INTVAL (operands[3]) + INTVAL (operands[4])
       >= GET_MODE_PRECISION (<MODE>mode)"
-- 
1.8.1.4

[PATCH 3/3] lt0_disi

[Segher Boessenkool]

After Kyrill's patch (r225996) (changing combine to do simplification
before doing some transformations) a shortcoming of the rs6000 backend
becomes obvious: we have no patterns to handle

	(set (reg:DI) (lt:DI (reg:SI) (const_int 0)))

although we can do that with a single rotate-and-mask instruction.
Previously, combine usually came up with a more complex pattern (that
we do implement), hiding the issue.

This patch adds a define_insn for the pattern.


2015-07-20  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md (*lt0_disi): New.

---
 gcc/config/rs6000/rs6000.md | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5727068..55ceb66 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3475,6 +3475,17 @@ (define_insn_and_split "*rotl<mode>3_mask_dot2"
    (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
+; Special case for less-than-0.  We can do it with just one machine
+; instruction, but the generic optimizers do not realise it is cheap.
+(define_insn "*lt0_disi"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(lt:DI (match_operand:SI 1 "gpc_reg_operand" "r")
+	       (const_int 0)))]
+  "TARGET_POWERPC64"
+  "rlwinm %0,%1,1,31,31"
+  [(set_attr "type" "shift")])
+
+
 
 ; Two forms for insert (the two arms of the IOR are not canonicalized,
 ; both are an AND so are the same precedence).
-- 
1.8.1.4

Re: [PATCH 1/3] Doc fixes for rot

[David Edelsohn]

On Mon, Jul 20, 2015 at 12:04 PM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> This removes the removed constraints from the documentation.  It also
> removes "q" (for MQ) which hasn't existed for a while.
>
>
> 2015-07-20  Segher Boessenkool  <segher@kernel.crashing.org>
>
>         * config/rs6000/constraints.md: Update "available letters" comment.
>         * doc/md.texi (Machine Constraints): Remove q, S, T, t constraints.

This is okay.

Thanks, David

Re: [PATCH 2/3] Fix shift amount (GPR->SI)

[David Edelsohn]

On Mon, Jul 20, 2015 at 12:04 PM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> This changes the shift amount to always be SI (as it should be), not GPR.
> It doesn't matter for constant shifts, but there are some variable shifts
> as well, and consistency is good.
>
> No changelog, I'll fold it into the previous big patch, if approved.

This is okay.

Thanks, David

Re: [PATCH 3/3] lt0_disi

[David Edelsohn]

On Mon, Jul 20, 2015 at 12:04 PM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> After Kyrill's patch (r225996) (changing combine to do simplification
> before doing some transformations) a shortcoming of the rs6000 backend
> becomes obvious: we have no patterns to handle
>
>         (set (reg:DI) (lt:DI (reg:SI) (const_int 0)))
>
> although we can do that with a single rotate-and-mask instruction.
> Previously, combine usually came up with a more complex pattern (that
> we do implement), hiding the issue.
>
> This patch adds a define_insn for the pattern.
>
>
> 2015-07-20  Segher Boessenkool  <segher@kernel.crashing.org>
>
>         * config/rs6000/rs6000.md (*lt0_disi): New.

This is okay.

Thanks, David