From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16314 invoked by alias); 29 May 2013 19:53:47 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 16301 invoked by uid 89); 29 May 2013 19:53:46 -0000 X-Spam-SWARE-Status: No, score=-3.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,KHOP_THREADED,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE,SPF_PASS autolearn=ham version=3.3.1 Received: from mail-ve0-f177.google.com (HELO mail-ve0-f177.google.com) (209.85.128.177) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Wed, 29 May 2013 19:53:46 +0000 Received: by mail-ve0-f177.google.com with SMTP id cz10so2544276veb.36 for ; Wed, 29 May 2013 12:53:44 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.220.252.10 with SMTP id mu10mr2740793vcb.4.1369857224182; Wed, 29 May 2013 12:53:44 -0700 (PDT) Received: by 10.220.175.131 with HTTP; Wed, 29 May 2013 12:53:43 -0700 (PDT) In-Reply-To: <20130522142533.GA25178@ibm-tiger.the-meissners.org> References: <20130520204053.GA21090@ibm-tiger.the-meissners.org> <20130522142533.GA25178@ibm-tiger.the-meissners.org> Date: Wed, 29 May 2013 19:53:00 -0000 Message-ID: Subject: Re: [PATCH, rs6000] power8 patches, patch #6, direct move & basic quad load/store From: David Edelsohn To: Michael Meissner , GCC Patches , David Edelsohn , Pat Haugen , Peter Bergner Content-Type: text/plain; charset=ISO-8859-1 X-SW-Source: 2013-05/txt/msg01745.txt.bz2 + if (TARGET_DIRECT_MOVE) + { + if (TARGET_POWERPC64) + { + reload_gpr_vsx[TImode] = CODE_FOR_reload_gpr_from_vsxti; + reload_gpr_vsx[V2DFmode] = CODE_FOR_reload_gpr_from_vsxv2df; + reload_gpr_vsx[V2DImode] = CODE_FOR_reload_gpr_from_vsxv2di; + reload_gpr_vsx[V4SFmode] = CODE_FOR_reload_gpr_from_vsxv4sf; + reload_gpr_vsx[V4SImode] = CODE_FOR_reload_gpr_from_vsxv4si; + reload_gpr_vsx[V8HImode] = CODE_FOR_reload_gpr_from_vsxv8hi; + reload_gpr_vsx[V16QImode] = CODE_FOR_reload_gpr_from_vsxv16qi; + reload_gpr_vsx[SFmode] = CODE_FOR_reload_gpr_from_vsxsf; + + reload_vsx_gpr[TImode] = CODE_FOR_reload_vsx_from_gprti; + reload_vsx_gpr[V2DFmode] = CODE_FOR_reload_vsx_from_gprv2df; + reload_vsx_gpr[V2DImode] = CODE_FOR_reload_vsx_from_gprv2di; + reload_vsx_gpr[V4SFmode] = CODE_FOR_reload_vsx_from_gprv4sf; + reload_vsx_gpr[V4SImode] = CODE_FOR_reload_vsx_from_gprv4si; + reload_vsx_gpr[V8HImode] = CODE_FOR_reload_vsx_from_gprv8hi; + reload_vsx_gpr[V16QImode] = CODE_FOR_reload_vsx_from_gprv16qi; + reload_vsx_gpr[SFmode] = CODE_FOR_reload_vsx_from_gprsf; + } + else + { + reload_fpr_gpr[DImode] = CODE_FOR_reload_fpr_from_gprdi; + reload_fpr_gpr[DDmode] = CODE_FOR_reload_fpr_from_gprdd; + reload_fpr_gpr[DFmode] = CODE_FOR_reload_fpr_from_gprdf; + } + } Why do the VSX reload functions depend on TARGET_POWERPC64? That seems like the wrong test. +/* Return true if this is a move direct operation between GPR registers and + floating point/VSX registers. */ + +bool +direct_move_p (rtx op0, rtx op1) Why isn't this function symmetric? It at least needs an explanation in the comment about assumptions for the operands. +/* Return true if this is a load or store quad operation. */ + +bool +quad_load_store_p (rtx op0, rtx op1) Same for this function. +/* Helper function for rs6000_secondary_reload to return true if a move to a + different register classe is really a simple move. */ + +static bool +rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type, + enum rs6000_reg_type from_type, + enum machine_mode mode) +{ + int size; + + /* Add support for various direct moves available. In this function, we only + look at cases where we don't need any extra registers, and one or more + simple move insns are issued. At present, 32-bit integers are not allowed + in FPR/VSX registers. Single precision binary floating is not a simple + move because we need to convert to the single precision memory layout. + The 4-byte SDmode can be moved. */ The second comment should be merged into the first -- it explains the purpose and implementation of the function. +/* Return whether a move between two register classes can be done either + directly (simple move) or via a pattern that uses a single extra temporary + (using power8's direct move in this case. */ + +static bool +rs6000_secondary_reload_move (enum rs6000_reg_type to_type, + enum rs6000_reg_type from_type, + enum machine_mode mode, + secondary_reload_info *sri, + bool altivec_p) Missing a close parenthesis in the comment. (define_insn "*vsx_mov" - [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,,,?Z,?wa,?wa,*Y,*r,*r,,?wa,*r,v,wZ,v") - (match_operand:VSX_M 1 "input_operand" ",Z,,wa,Z,wa,r,Y,r,j,j,j,W,v,wZ"))] + [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,,,?Z,?wa,?wa,wQ,?&r,??Y,??r,??r,,?wa,*r,v,wZ, v") + (match_operand:VSX_M 1 "input_operand" ",Z,,wa,Z,wa,r,wQ,r,Y,r,j,j,j,W,v,wZ"))] Why do you need to change the modifiers? Why should vector operands in GPRs matter for register preferences (removing `*' from "r" constraints)? Thanks, David