From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 6854 invoked by alias); 12 Jun 2013 21:55:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 6817 invoked by uid 89); 12 Jun 2013 21:55:45 -0000 X-Spam-SWARE-Status: No, score=-3.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,KHOP_THREADED,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE,SPF_PASS autolearn=ham version=3.3.1 Received: from mail-ve0-f174.google.com (HELO mail-ve0-f174.google.com) (209.85.128.174) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Wed, 12 Jun 2013 21:55:44 +0000 Received: by mail-ve0-f174.google.com with SMTP id oz10so7215942veb.33 for ; Wed, 12 Jun 2013 14:55:42 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.52.164.163 with SMTP id yr3mr8845713vdb.76.1371074142748; Wed, 12 Jun 2013 14:55:42 -0700 (PDT) Received: by 10.220.118.135 with HTTP; Wed, 12 Jun 2013 14:55:42 -0700 (PDT) In-Reply-To: <20130611235334.GA20069@ibm-tiger.the-meissners.org> References: <20130520204053.GA21090@ibm-tiger.the-meissners.org> <20130522164952.GA14241@ibm-tiger.the-meissners.org> <20130611235334.GA20069@ibm-tiger.the-meissners.org> Date: Wed, 12 Jun 2013 21:55:00 -0000 Message-ID: Subject: Re: [PATCH, rs6000] power8 patches, patch #7, quad/byte/half-word atomic instructions From: David Edelsohn To: Michael Meissner , David Edelsohn , GCC Patches , Pat Haugen , Peter Bergner Content-Type: text/plain; charset=ISO-8859-1 X-SW-Source: 2013-06/txt/msg00749.txt.bz2 On Tue, Jun 11, 2013 at 7:53 PM, Michael Meissner wrote: > I needed to rework the sync.md so that it would work correctly with no > optimization (using SUBREG's at -O0 did not give us the even registers for > holding PTImode values, so I created a PTImode temporary in load_lockedti and > store_conditionalti, which is normally optimized out. > > [gcc] > 2013-06-11 Michael Meissner > Pat Haugen > Peter Bergner > > * config/rs6000/rs6000.c (emit_load_locked): Add support for > power8 byte, half-word, and quad-word atomic instructions. > (emit_store_conditional): Likewise. > (rs6000_expand_atomic_compare_and_swap): Likewise. > (rs6000_expand_atomic_op): Likewise. > > * config/rs6000/sync.md (larx): Add new modes for power8. > (stcx): Likewise. > (AINT): New mode iterator to include TImode as well as normal > integer modes on power8. > (fetchop_pred): Use int_reg_operand instead of gpc_reg_operand so > that VSX registers are not considered. Use AINT mode iterator > instead of INT1 to allow inclusion of quad word atomic operations > on power8. > (load_locked): Likewise. > (store_conditional): Likewise. > (atomic_compare_and_swap): Likewise. > (atomic_exchange): Likewise. > (atomic_nand): Likewise. > (atomic_fetch_): Likewise. > (atomic_nand_fetch): Likewise. > (mem_thread_fence): Use gen_loadsync_ instead of enumerating > each type. > (ATOMIC): On power8, add QImode, HImode modes. > (load_locked_si): Varients of load_locked for QI/HI > modes that promote to SImode. > (load_lockedti): Convert TImode arguments to PTImode, so that we > get a guaranteed even/odd register pair. > (load_lockedpti): Likewise. > (store_conditionalti): Likewise. > (store_conditionalpti): Likewise. > > * config/rs6000/rs6000.md (QHI): New mode iterator for power8 > atomic load/store instructions. > (HSI): Likewise. > > [gcc/testsuite] > 2013-06-11 Michael Meissner > Pat Haugen > Peter Bergner > > * gcc.target/powerpc/atomic-p7.c: New file, add tests for atomic > load/store instructions on power7, power8. > * gcc.target/powerpc/atomic-p8.c: Likewise. > > Given these changes went beyond the original request to fix a spelling error > and improve the logic, I figured to send these patches out again. David, do > you have any problem with the new patches? The new patches are okay. Thanks for re-checking. Thanks, David