From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by sourceware.org (Postfix) with ESMTPS id F09873851C12; Tue, 14 Jul 2020 14:17:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org F09873851C12 Received: by mail-wr1-x442.google.com with SMTP id a6so21915356wrm.4; Tue, 14 Jul 2020 07:17:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=E6sGxO9duLc/ooZ8ySEXIcR0B/PzpfmuDP3WCeGyuhY=; b=OttbPRN7sA/pp1i6jF/VwAr0LdEMvpji5yx34wpSRtGSN1yOB7kvkoYCfEBThoyccP +T5sTid8fCy1H2fYI6eJTiueFk6Lx+7NinxZIGm8fLRtmS80dYbPzLHteY1XChaKIJIS vN4Dd6/zkSMoUtf+z3+lWb0BcEXbFVfNui3WOo0Oxsf6rlhNz0pH/jr+R6+CiFoQEzil Sw+nx+RJZUBIpAwKqW8CsISeu72imjTY2AliDUfiW9Ihb1mQHNWKzsLC6mrMsfznYpzc 1BpCI20CdNhqux5ycOVNzoSQa7M/fgjpYqxaOZ7gDUwT+044mfT9FhmfUcYbyp7bM2+C 2eNw== X-Gm-Message-State: AOAM533TeAY37CWg6Tn5d5NQ/Gb9kgORXVM86fYOcFV43bzO2rVU5Ufj AXQcUQfTvYS1vJEgmo3hOu6USm/eQt0flRcWkJrhR8n8 X-Google-Smtp-Source: ABdhPJxU/DaNOxx9/6hV6EUitWDclGFU3l5vbPa41F7DN7N9tMsWyygtMc0BiYO46tXOPpqoLIq+yMQXNtLpwgx6f80= X-Received: by 2002:a5d:538e:: with SMTP id d14mr5877791wrv.21.1594736239884; Tue, 14 Jul 2020 07:17:19 -0700 (PDT) MIME-Version: 1.0 References: <20200706021757.1118129-1-luoxhu@linux.ibm.com> <20200707001803.GR3598@gate.crashing.org> <66c7b5d6-afa6-53d7-704d-44834ff00311@linux.ibm.com> <20200707213116.GU3598@gate.crashing.org> <66faac54-0620-5ee0-ff48-5609ad9e3fa7@linux.ibm.com> <20200708224334.GY3598@gate.crashing.org> <20200709192515.GO3598@gate.crashing.org> <472e0dc4-6fc6-8d0b-2c0c-259dccd29a89@linux.ibm.com> <20200711005438.GE30544@gate.crashing.org> <49363e95-d454-d9af-24aa-45f641da29fa@linux.ibm.com> In-Reply-To: <49363e95-d454-d9af-24aa-45f641da29fa@linux.ibm.com> From: David Edelsohn Date: Tue, 14 Jul 2020 10:17:08 -0400 Message-ID: Subject: Re: [PATCH] rs6000: Define movsf_from_si2 to extract high part SF element from DImode[PR89310] To: luoxhu Cc: Segher Boessenkool , GCC Patches , Bill Schmidt , guojiufu , linkw@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-6.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Jul 2020 14:17:22 -0000 Unfortunately this patch is eliciting a number of new testsuite failures, all like error: unrecognizable insn: (insn 44 43 45 5 (parallel [ (set (reg:SI 199) (unspec:SI [ (reg:SF 202) ] UNSPEC_SI_FROM_SF)) (clobber (scratch:V4SF)) ]) "/nasfarm/edelsohn/src/src/gcc/testsuite/gcc.dg/vect/vect-alias-check-11.c":70:1 -1 (nil)) during RTL pass: vregs for gcc.dg/vect/vect-alias-check-11.c gcc.dg/vect/vect-alias-check-12.c gcc.dg/vect/pr57741-2.c gcc.dg/vect/pr57741-3.c gcc.dg/vect/pr89440.c gcc.target/powerpc/sse-movss-1.c Thanks, David On Mon, Jul 13, 2020 at 2:30 AM luoxhu wrote: > > Hi, > > On 2020/7/11 08:54, Segher Boessenkool wrote: > > Hi! > > > > On Fri, Jul 10, 2020 at 09:39:40AM +0800, luoxhu wrote: > >> OK, seems the md file needs a format tool too... > > > > Heh. Just make sure it looks good (that is, does what it looks like), > > looks like the rest, etc. It's hard to do anything nice with unspecs, > > [ ] lists do not format well. > > > >>>> + "TARGET_NO_SF_SUBREG" > >>>> + "#" > >>>> + "&& vsx_reg_sfsubreg_ok (operands[0], SFmode)" > >>> > >>> Put this in the insn condition? And since this is just a predicate, > >>> you can just use it instead of gpc_reg_operand. > >>> > >>> (The split condition becomes "&& 1" then, not ""). > >> > >> OK, this seems a bit strange as movsi_from_sf, movsf_from_si and > >> movdi_from_sf_zero_ext all use it as condition... > > > > Since in your case you *always* split, the split condition should be > > "always". There are no alternatives that do not split here. > > > >> And why vsx_reg_sfsubreg_ok allows "SF SUBREGS" and TARGET_NO_SF_SUBREG > >> "avoid (SUBREG:SF (REG:SI)", I guess they are not the same meaning? (The > >> TARGET_NO_SF_SUBREG is also copied from other similar defines.) Thanks. > > > > Good question. I do not know. > > > > Well... Since this define_insn* requires p8 *anyway*, we do not need > > any of these sf_subreg things? We always know for each one if it should > > be true or false. > > Yes, removed the vsx_reg_sfsubreg_ok check. > > > > >> + "TARGET_NO_SF_SUBREG" > > > > But here we should require p8 some other way, then. > > TARGET_NO_SF_SUBREG is defined to TARGET_DIRECT_MOVE_64BIT, and > TARGET_DIRECT_MOVE_64BIT is TARGET_DIRECT_MOVE && TARGET_P8_VECTOR && TARGET_POWERPC64 > which means TARGET_P8_VECTOR must be true for TARGET_NO_SF_SUBREG. > > > > >> + (set_attr "isa" "p8v")]) > > > > (This isn't enough, unfortunately). > > > > > Updated patch to removed the vsx_reg_sfsubreg_ok and ICE fix: > > > For extracting high part element from DImode register like: > > {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;} > > split it before reload with "and mask" to avoid generating shift right > 32 bit then shift left 32 bit. This pattern also exists in PR42475 and > PR67741, etc. > > srdi 3,3,32 > sldi 9,3,32 > mtvsrd 1,9 > xscvspdpn 1,1 > > => > > rldicr 3,3,0,31 > mtvsrd 1,3 > xscvspdpn 1,1 > > Bootstrap and regression tested pass on Power8-LE. > > gcc/ChangeLog: > > 2020-07-13 Xionghu Luo > > PR rtl-optimization/89310 > * config/rs6000/rs6000.md (movsf_from_si2): New > define_insn_and_split. > > gcc/testsuite/ChangeLog: > > 2020-07-13 Xionghu Luo > > PR rtl-optimization/89310 > * gcc.target/powerpc/pr89310.c: New test. > --- > gcc/config/rs6000/rs6000.md | 31 ++++++++++++++++++++++ > gcc/testsuite/gcc.target/powerpc/pr89310.c | 17 ++++++++++++ > 2 files changed, 48 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/powerpc/pr89310.c > > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md > index 4fcd6a94022..480385ed4d2 100644 > --- a/gcc/config/rs6000/rs6000.md > +++ b/gcc/config/rs6000/rs6000.md > @@ -7593,6 +7593,37 @@ (define_insn_and_split "movsf_from_si" > "*, *, p9v, p8v, *, *, > p8v, p8v, p8v, *")]) > > +;; For extracting high part element from DImode register like: > +;; {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;} > +;; split it before reload with "and mask" to avoid generating shift right > +;; 32 bit then shift left 32 bit. > +(define_insn_and_split "movsf_from_si2" > + [(set (match_operand:SF 0 "gpc_reg_operand" "=wa") > + (unspec:SF > + [(subreg:SI > + (ashiftrt:DI > + (match_operand:DI 1 "input_operand" "r") > + (const_int 32)) > + 0)] > + UNSPEC_SF_FROM_SI)) > + (clobber (match_scratch:DI 2 "=r"))] > + "TARGET_NO_SF_SUBREG" > + "#" > + "&& 1" > + [(const_int 0)] > +{ > + if (GET_CODE (operands[2]) == SCRATCH) > + operands[2] = gen_reg_rtx (DImode); > + > + rtx mask = GEN_INT (HOST_WIDE_INT_M1U << 32); > + emit_insn (gen_anddi3 (operands[2], operands[1], mask)); > + emit_insn (gen_p8_mtvsrd_sf (operands[0], operands[2])); > + emit_insn (gen_vsx_xscvspdpn_directmove (operands[0], operands[0])); > + DONE; > +} > + [(set_attr "length" "12") > + (set_attr "type" "vecfloat") > + (set_attr "isa" "p8v")]) > > ;; Move 64-bit binary/decimal floating point > (define_expand "mov" > diff --git a/gcc/testsuite/gcc.target/powerpc/pr89310.c b/gcc/testsuite/gcc.target/powerpc/pr89310.c > new file mode 100644 > index 00000000000..15e78509246 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr89310.c > @@ -0,0 +1,17 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2" } */ > + > +struct s { > + int i; > + float f; > +}; > + > +float > +foo (struct s arg) > +{ > + return arg.f; > +} > + > +/* { dg-final { scan-assembler-not {\msrdi\M} } } */ > +/* { dg-final { scan-assembler-not {\msldi\M} } } */ > +/* { dg-final { scan-assembler-times {\mrldicr\M} 1 } } */ > -- > 2.21.0.777.g83232e3864 > >