* [PATCH V5 1/2] rs6000: optimize moving to sf from highpart di
@ 2023-10-05 4:13 Jiufu Guo
2023-10-05 4:13 ` [PATCH V5 2/2] rs6000: use mtvsrws to move sf from si p9 Jiufu Guo
2023-10-05 16:52 ` [PATCH V5 1/2] rs6000: optimize moving to sf from highpart di David Edelsohn
0 siblings, 2 replies; 6+ messages in thread
From: Jiufu Guo @ 2023-10-05 4:13 UTC (permalink / raw)
To: gcc-patches; +Cc: segher, dje.gcc, linkw, bergner, guojiufu
Hi,
Currently, we have the pattern "movsf_from_si2" which was trying
to support moving high part DI to SF.
But current pattern only accepts "ashiftrt":
XX:SF=bitcast:SF(subreg(YY:DI>>32),0), but actually "lshiftrt" should
also be ok.
And current pattern only supports BE.
This patch updats the pattern to support BE and "lshiftrt".
Compare with previous version:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628790.html
This version refines the code slightly and updates the test case
according to review comments.
Pass bootstrap and regtest on ppc64{,le}.
Is this ok for trunk?
BR,
Jeff (Jiufu Guo)
PR target/108338
gcc/ChangeLog:
* config/rs6000/predicates.md (lowpart_subreg_operator): New
define_predicate.
* config/rs6000/rs6000.md (any_rshift): New code_iterator.
(movsf_from_si2): Rename to ...
(movsf_from_si2_<code>): ... this.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/pr108338.c: New test.
---
gcc/config/rs6000/predicates.md | 5 +++
gcc/config/rs6000/rs6000.md | 12 ++++---
gcc/testsuite/gcc.target/powerpc/pr108338.c | 37 +++++++++++++++++++++
3 files changed, 49 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108338.c
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 925f69cd3fc..ef7d3f214c4 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -2098,3 +2098,8 @@ (define_predicate "macho_pic_address"
else
return false;
})
+
+(define_predicate "lowpart_subreg_operator"
+ (and (match_code "subreg")
+ (match_test "subreg_lowpart_offset (mode, GET_MODE (SUBREG_REG (op)))
+ == SUBREG_BYTE (op)")))
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1a9a7b1a479..56bd8bc1147 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -643,6 +643,9 @@ (define_code_iterator any_extend [sign_extend zero_extend])
(define_code_iterator any_fix [fix unsigned_fix])
(define_code_iterator any_float [float unsigned_float])
+; Shift right.
+(define_code_iterator any_shiftrt [ashiftrt lshiftrt])
+
(define_code_attr u [(sign_extend "")
(zero_extend "u")
(fix "")
@@ -8303,14 +8306,13 @@ (define_insn_and_split "movsf_from_si"
;; {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;}
;; split it before reload with "and mask" to avoid generating shift right
;; 32 bit then shift left 32 bit.
-(define_insn_and_split "movsf_from_si2"
+(define_insn_and_split "movsf_from_si2_<code>"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
(unspec:SF
- [(subreg:SI
- (ashiftrt:DI
+ [(match_operator:SI 3 "lowpart_subreg_operator"
+ [(any_shiftrt:DI
(match_operand:DI 1 "input_operand" "r")
- (const_int 32))
- 0)]
+ (const_int 32))])]
UNSPEC_SF_FROM_SI))
(clobber (match_scratch:DI 2 "=r"))]
"TARGET_NO_SF_SUBREG"
diff --git a/gcc/testsuite/gcc.target/powerpc/pr108338.c b/gcc/testsuite/gcc.target/powerpc/pr108338.c
new file mode 100644
index 00000000000..bd83c0b3ad8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr108338.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target hard_float } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* Under lp64, parameter 'v' is in DI regs, then bitcast sub DI to SF. */
+/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
+/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
+/* { dg-final { scan-assembler-times {\mrldicr\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
+
+struct di_sf_sf
+{
+ float f1; float f2; long long l;
+};
+
+float __attribute__ ((noipa))
+sf_from_high32bit_di (struct di_sf_sf v)
+{
+#ifdef __LITTLE_ENDIAN__
+ return v.f2;
+#else
+ return v.f1;
+#endif
+}
+
+int main()
+{
+ struct di_sf_sf v;
+ v.f1 = v.f2 = 0.0f;
+#ifdef __LITTLE_ENDIAN__
+ v.f2 = 2.0f;
+#else
+ v.f1 = 2.0f;
+#endif
+ if (sf_from_high32bit_di (v) != 2.0f)
+ __builtin_abort ();
+ return 0;
+}
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V5 2/2] rs6000: use mtvsrws to move sf from si p9
2023-10-05 4:13 [PATCH V5 1/2] rs6000: optimize moving to sf from highpart di Jiufu Guo
@ 2023-10-05 4:13 ` Jiufu Guo
2023-10-05 16:54 ` David Edelsohn
2023-10-05 16:52 ` [PATCH V5 1/2] rs6000: optimize moving to sf from highpart di David Edelsohn
1 sibling, 1 reply; 6+ messages in thread
From: Jiufu Guo @ 2023-10-05 4:13 UTC (permalink / raw)
To: gcc-patches; +Cc: segher, dje.gcc, linkw, bergner, guojiufu
Hi,
As mentioned in PR108338, on p9, we could use mtvsrws to implement
the bitcast from SI to SF (or lowpart DI to SF).
For example:
*(long long*)buff = di;
float f = *(float*)(buff);
"sldi 9,3,32 ; mtvsrd 1,9 ; xscvspdpn 1,1" is generated.
A better one would be "mtvsrws 1,3 ; xscvspdpn 1,1".
Compare with previous patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628791.html
According to review comments, this version refines commit message
and words in comments, also updates the test case
Pass bootstrap and regtest on ppc64{,le}.
Is this ok for trunk?
BR,
Jeff (Jiufu Guo)
PR target/108338
gcc/ChangeLog:
* config/rs6000/rs6000.md (movsf_from_si): Update to generate mtvsrws
for P9.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/pr108338.c: Updated to check mtvsrws for p9.
---
gcc/config/rs6000/rs6000.md | 25 ++++++++++++++++-----
gcc/testsuite/gcc.target/powerpc/pr108338.c | 21 ++++++++++++++---
2 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 56bd8bc1147..d6dfb25cea0 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8283,13 +8283,26 @@ (define_insn_and_split "movsf_from_si"
{
rtx op0 = operands[0];
rtx op1 = operands[1];
- rtx op2 = operands[2];
- rtx op1_di = gen_rtx_REG (DImode, REGNO (op1));
- /* Move SF value to upper 32-bits for xscvspdpn. */
- emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
- emit_insn (gen_p8_mtvsrd_sf (op0, op2));
- emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
+ /* Move lowpart 32-bits from register for SFmode. */
+ if (TARGET_P9_VECTOR)
+ {
+ /* Using mtvsrws;xscvspdpn. */
+ rtx op0_v = gen_rtx_REG (V4SImode, REGNO (op0));
+ emit_insn (gen_vsx_splat_v4si (op0_v, op1));
+ emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
+ }
+ else
+ {
+ rtx op2 = operands[2];
+ rtx op1_di = gen_rtx_REG (DImode, REGNO (op1));
+
+ /* Using sldi;mtvsrd;xscvspdpn. */
+ emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
+ emit_insn (gen_p8_mtvsrd_sf (op0, op2));
+ emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
+ }
+
DONE;
}
[(set_attr "length"
diff --git a/gcc/testsuite/gcc.target/powerpc/pr108338.c b/gcc/testsuite/gcc.target/powerpc/pr108338.c
index bd83c0b3ad8..5f2f62866ee 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr108338.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr108338.c
@@ -3,9 +3,12 @@
/* { dg-options "-O2 -save-temps" } */
/* Under lp64, parameter 'v' is in DI regs, then bitcast sub DI to SF. */
-/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
-/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
+/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 2 { target { lp64 && has_arch_pwr8 } } } } */
+/* { dg-final { scan-assembler-times {\mmtvsrd\M} 2 { target { lp64 && { has_arch_pwr8 && { ! has_arch_pwr9 } } } } } } */
+/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 && has_arch_pwr9 } } } } */
+/* { dg-final { scan-assembler-times {\mmtvsrws\M} 1 { target { lp64 && has_arch_pwr9 } } } } */
/* { dg-final { scan-assembler-times {\mrldicr\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
+/* { dg-final { scan-assembler-times {\msldi\M} 1 { target { lp64 && { has_arch_pwr8 && { ! has_arch_pwr9 } } } } } } */
struct di_sf_sf
{
@@ -22,16 +25,28 @@ sf_from_high32bit_di (struct di_sf_sf v)
#endif
}
+float __attribute__ ((noipa))
+sf_from_low32bit_di (struct di_sf_sf v)
+{
+#ifdef __LITTLE_ENDIAN__
+ return v.f1;
+#else
+ return v.f2;
+#endif
+}
+
int main()
{
struct di_sf_sf v;
v.f1 = v.f2 = 0.0f;
#ifdef __LITTLE_ENDIAN__
+ v.f1 = 1.0f;
v.f2 = 2.0f;
#else
v.f1 = 2.0f;
+ v.f2 = 1.0f;
#endif
- if (sf_from_high32bit_di (v) != 2.0f)
+ if (sf_from_high32bit_di (v) != 2.0f || sf_from_low32bit_di (v) != 1.0f)
__builtin_abort ();
return 0;
}
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V5 1/2] rs6000: optimize moving to sf from highpart di
2023-10-05 4:13 [PATCH V5 1/2] rs6000: optimize moving to sf from highpart di Jiufu Guo
2023-10-05 4:13 ` [PATCH V5 2/2] rs6000: use mtvsrws to move sf from si p9 Jiufu Guo
@ 2023-10-05 16:52 ` David Edelsohn
2023-10-07 8:01 ` Jiufu Guo
1 sibling, 1 reply; 6+ messages in thread
From: David Edelsohn @ 2023-10-05 16:52 UTC (permalink / raw)
To: Jiufu Guo; +Cc: gcc-patches, segher, linkw, bergner
[-- Attachment #1: Type: text/plain, Size: 4851 bytes --]
On Thu, Oct 5, 2023 at 12:50 AM Jiufu Guo <guojiufu@linux.ibm.com> wrote:
> Hi,
>
> Currently, we have the pattern "movsf_from_si2" which was trying
> to support moving high part DI to SF.
>
> But current pattern only accepts "ashiftrt":
> XX:SF=bitcast:SF(subreg(YY:DI>>32),0), but actually "lshiftrt" should
> also be ok.
> And current pattern only supports BE.
>
> This patch updats the pattern to support BE and "lshiftrt".
>
> Compare with previous version:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628790.html
> This version refines the code slightly and updates the test case
> according to review comments.
>
> Pass bootstrap and regtest on ppc64{,le}.
> Is this ok for trunk?
>
Okay.
Thanks, David
>
> BR,
> Jeff (Jiufu Guo)
>
> PR target/108338
>
> gcc/ChangeLog:
>
> * config/rs6000/predicates.md (lowpart_subreg_operator): New
> define_predicate.
> * config/rs6000/rs6000.md (any_rshift): New code_iterator.
> (movsf_from_si2): Rename to ...
> (movsf_from_si2_<code>): ... this.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/powerpc/pr108338.c: New test.
>
> ---
> gcc/config/rs6000/predicates.md | 5 +++
> gcc/config/rs6000/rs6000.md | 12 ++++---
> gcc/testsuite/gcc.target/powerpc/pr108338.c | 37 +++++++++++++++++++++
> 3 files changed, 49 insertions(+), 5 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108338.c
>
> diff --git a/gcc/config/rs6000/predicates.md
> b/gcc/config/rs6000/predicates.md
> index 925f69cd3fc..ef7d3f214c4 100644
> --- a/gcc/config/rs6000/predicates.md
> +++ b/gcc/config/rs6000/predicates.md
> @@ -2098,3 +2098,8 @@ (define_predicate "macho_pic_address"
> else
> return false;
> })
> +
> +(define_predicate "lowpart_subreg_operator"
> + (and (match_code "subreg")
> + (match_test "subreg_lowpart_offset (mode, GET_MODE (SUBREG_REG
> (op)))
> + == SUBREG_BYTE (op)")))
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 1a9a7b1a479..56bd8bc1147 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -643,6 +643,9 @@ (define_code_iterator any_extend [sign_extend
> zero_extend])
> (define_code_iterator any_fix [fix unsigned_fix])
> (define_code_iterator any_float [float unsigned_float])
>
> +; Shift right.
> +(define_code_iterator any_shiftrt [ashiftrt lshiftrt])
> +
> (define_code_attr u [(sign_extend "")
> (zero_extend "u")
> (fix "")
> @@ -8303,14 +8306,13 @@ (define_insn_and_split "movsf_from_si"
> ;; {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;}
> ;; split it before reload with "and mask" to avoid generating shift right
> ;; 32 bit then shift left 32 bit.
> -(define_insn_and_split "movsf_from_si2"
> +(define_insn_and_split "movsf_from_si2_<code>"
> [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
> (unspec:SF
> - [(subreg:SI
> - (ashiftrt:DI
> + [(match_operator:SI 3 "lowpart_subreg_operator"
> + [(any_shiftrt:DI
> (match_operand:DI 1 "input_operand" "r")
> - (const_int 32))
> - 0)]
> + (const_int 32))])]
> UNSPEC_SF_FROM_SI))
> (clobber (match_scratch:DI 2 "=r"))]
> "TARGET_NO_SF_SUBREG"
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr108338.c
> b/gcc/testsuite/gcc.target/powerpc/pr108338.c
> new file mode 100644
> index 00000000000..bd83c0b3ad8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr108338.c
> @@ -0,0 +1,37 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target hard_float } */
> +/* { dg-options "-O2 -save-temps" } */
> +
> +/* Under lp64, parameter 'v' is in DI regs, then bitcast sub DI to SF. */
> +/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 1 { target { lp64 &&
> has_arch_pwr8 } } } } */
> +/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 &&
> has_arch_pwr8 } } } } */
> +/* { dg-final { scan-assembler-times {\mrldicr\M} 1 { target { lp64 &&
> has_arch_pwr8 } } } } */
> +
> +struct di_sf_sf
> +{
> + float f1; float f2; long long l;
> +};
> +
> +float __attribute__ ((noipa))
> +sf_from_high32bit_di (struct di_sf_sf v)
> +{
> +#ifdef __LITTLE_ENDIAN__
> + return v.f2;
> +#else
> + return v.f1;
> +#endif
> +}
> +
> +int main()
> +{
> + struct di_sf_sf v;
> + v.f1 = v.f2 = 0.0f;
> +#ifdef __LITTLE_ENDIAN__
> + v.f2 = 2.0f;
> +#else
> + v.f1 = 2.0f;
> +#endif
> + if (sf_from_high32bit_di (v) != 2.0f)
> + __builtin_abort ();
> + return 0;
> +}
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V5 2/2] rs6000: use mtvsrws to move sf from si p9
2023-10-05 4:13 ` [PATCH V5 2/2] rs6000: use mtvsrws to move sf from si p9 Jiufu Guo
@ 2023-10-05 16:54 ` David Edelsohn
2023-10-07 8:00 ` Jiufu Guo
0 siblings, 1 reply; 6+ messages in thread
From: David Edelsohn @ 2023-10-05 16:54 UTC (permalink / raw)
To: Jiufu Guo; +Cc: gcc-patches, segher, linkw, bergner
[-- Attachment #1: Type: text/plain, Size: 4581 bytes --]
On Thu, Oct 5, 2023 at 12:14 AM Jiufu Guo <guojiufu@linux.ibm.com> wrote:
> Hi,
>
> As mentioned in PR108338, on p9, we could use mtvsrws to implement
> the bitcast from SI to SF (or lowpart DI to SF).
>
> For example:
> *(long long*)buff = di;
> float f = *(float*)(buff);
>
> "sldi 9,3,32 ; mtvsrd 1,9 ; xscvspdpn 1,1" is generated.
> A better one would be "mtvsrws 1,3 ; xscvspdpn 1,1".
>
> Compare with previous patch:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628791.html
> According to review comments, this version refines commit message
> and words in comments, also updates the test case
>
> Pass bootstrap and regtest on ppc64{,le}.
> Is this ok for trunk?
>
Okay.
Thanks, David
>
> BR,
> Jeff (Jiufu Guo)
>
> PR target/108338
>
> gcc/ChangeLog:
>
> * config/rs6000/rs6000.md (movsf_from_si): Update to generate
> mtvsrws
> for P9.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/powerpc/pr108338.c: Updated to check mtvsrws for p9.
>
> ---
> gcc/config/rs6000/rs6000.md | 25 ++++++++++++++++-----
> gcc/testsuite/gcc.target/powerpc/pr108338.c | 21 ++++++++++++++---
> 2 files changed, 37 insertions(+), 9 deletions(-)
>
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 56bd8bc1147..d6dfb25cea0 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -8283,13 +8283,26 @@ (define_insn_and_split "movsf_from_si"
> {
> rtx op0 = operands[0];
> rtx op1 = operands[1];
> - rtx op2 = operands[2];
> - rtx op1_di = gen_rtx_REG (DImode, REGNO (op1));
>
> - /* Move SF value to upper 32-bits for xscvspdpn. */
> - emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
> - emit_insn (gen_p8_mtvsrd_sf (op0, op2));
> - emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
> + /* Move lowpart 32-bits from register for SFmode. */
> + if (TARGET_P9_VECTOR)
> + {
> + /* Using mtvsrws;xscvspdpn. */
> + rtx op0_v = gen_rtx_REG (V4SImode, REGNO (op0));
> + emit_insn (gen_vsx_splat_v4si (op0_v, op1));
> + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
> + }
> + else
> + {
> + rtx op2 = operands[2];
> + rtx op1_di = gen_rtx_REG (DImode, REGNO (op1));
> +
> + /* Using sldi;mtvsrd;xscvspdpn. */
> + emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
> + emit_insn (gen_p8_mtvsrd_sf (op0, op2));
> + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
> + }
> +
> DONE;
> }
> [(set_attr "length"
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr108338.c
> b/gcc/testsuite/gcc.target/powerpc/pr108338.c
> index bd83c0b3ad8..5f2f62866ee 100644
> --- a/gcc/testsuite/gcc.target/powerpc/pr108338.c
> +++ b/gcc/testsuite/gcc.target/powerpc/pr108338.c
> @@ -3,9 +3,12 @@
> /* { dg-options "-O2 -save-temps" } */
>
> /* Under lp64, parameter 'v' is in DI regs, then bitcast sub DI to SF. */
> -/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 1 { target { lp64 &&
> has_arch_pwr8 } } } } */
> -/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 &&
> has_arch_pwr8 } } } } */
> +/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 2 { target { lp64 &&
> has_arch_pwr8 } } } } */
> +/* { dg-final { scan-assembler-times {\mmtvsrd\M} 2 { target { lp64 && {
> has_arch_pwr8 && { ! has_arch_pwr9 } } } } } } */
> +/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 &&
> has_arch_pwr9 } } } } */
> +/* { dg-final { scan-assembler-times {\mmtvsrws\M} 1 { target { lp64 &&
> has_arch_pwr9 } } } } */
> /* { dg-final { scan-assembler-times {\mrldicr\M} 1 { target { lp64 &&
> has_arch_pwr8 } } } } */
> +/* { dg-final { scan-assembler-times {\msldi\M} 1 { target { lp64 && {
> has_arch_pwr8 && { ! has_arch_pwr9 } } } } } } */
>
> struct di_sf_sf
> {
> @@ -22,16 +25,28 @@ sf_from_high32bit_di (struct di_sf_sf v)
> #endif
> }
>
> +float __attribute__ ((noipa))
> +sf_from_low32bit_di (struct di_sf_sf v)
> +{
> +#ifdef __LITTLE_ENDIAN__
> + return v.f1;
> +#else
> + return v.f2;
> +#endif
> +}
> +
> int main()
> {
> struct di_sf_sf v;
> v.f1 = v.f2 = 0.0f;
> #ifdef __LITTLE_ENDIAN__
> + v.f1 = 1.0f;
> v.f2 = 2.0f;
> #else
> v.f1 = 2.0f;
> + v.f2 = 1.0f;
> #endif
> - if (sf_from_high32bit_di (v) != 2.0f)
> + if (sf_from_high32bit_di (v) != 2.0f || sf_from_low32bit_di (v) != 1.0f)
> __builtin_abort ();
> return 0;
> }
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V5 2/2] rs6000: use mtvsrws to move sf from si p9
2023-10-05 16:54 ` David Edelsohn
@ 2023-10-07 8:00 ` Jiufu Guo
0 siblings, 0 replies; 6+ messages in thread
From: Jiufu Guo @ 2023-10-07 8:00 UTC (permalink / raw)
To: David Edelsohn; +Cc: gcc-patches, segher, linkw, bergner
Hi,
David Edelsohn <dje.gcc@gmail.com> writes:
> This Message Is From an External Sender
> This message came from outside your organization.
> Report Suspicious
>
> On Thu, Oct 5, 2023 at 12:14 AM Jiufu Guo <guojiufu@linux.ibm.com> wrote:
>
> Hi,
>
> As mentioned in PR108338, on p9, we could use mtvsrws to implement
> the bitcast from SI to SF (or lowpart DI to SF).
>
> For example:
> *(long long*)buff = di;
> float f = *(float*)(buff);
>
> "sldi 9,3,32 ; mtvsrd 1,9 ; xscvspdpn 1,1" is generated.
> A better one would be "mtvsrws 1,3 ; xscvspdpn 1,1".
>
> Compare with previous patch:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628791.html
> According to review comments, this version refines commit message
> and words in comments, also updates the test case
>
> Pass bootstrap and regtest on ppc64{,le}.
> Is this ok for trunk?
>
> Okay.
Thank you! Committed as r14-4445.
BR,
Jeff.
>
> Thanks, David
>
>
> BR,
> Jeff (Jiufu Guo)
>
> PR target/108338
>
> gcc/ChangeLog:
>
> * config/rs6000/rs6000.md (movsf_from_si): Update to generate mtvsrws
> for P9.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/powerpc/pr108338.c: Updated to check mtvsrws for p9.
>
> ---
> gcc/config/rs6000/rs6000.md | 25 ++++++++++++++++-----
> gcc/testsuite/gcc.target/powerpc/pr108338.c | 21 ++++++++++++++---
> 2 files changed, 37 insertions(+), 9 deletions(-)
>
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 56bd8bc1147..d6dfb25cea0 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -8283,13 +8283,26 @@ (define_insn_and_split "movsf_from_si"
> {
> rtx op0 = operands[0];
> rtx op1 = operands[1];
> - rtx op2 = operands[2];
> - rtx op1_di = gen_rtx_REG (DImode, REGNO (op1));
>
> - /* Move SF value to upper 32-bits for xscvspdpn. */
> - emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
> - emit_insn (gen_p8_mtvsrd_sf (op0, op2));
> - emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
> + /* Move lowpart 32-bits from register for SFmode. */
> + if (TARGET_P9_VECTOR)
> + {
> + /* Using mtvsrws;xscvspdpn. */
> + rtx op0_v = gen_rtx_REG (V4SImode, REGNO (op0));
> + emit_insn (gen_vsx_splat_v4si (op0_v, op1));
> + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
> + }
> + else
> + {
> + rtx op2 = operands[2];
> + rtx op1_di = gen_rtx_REG (DImode, REGNO (op1));
> +
> + /* Using sldi;mtvsrd;xscvspdpn. */
> + emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
> + emit_insn (gen_p8_mtvsrd_sf (op0, op2));
> + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
> + }
> +
> DONE;
> }
> [(set_attr "length"
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr108338.c b/gcc/testsuite/gcc.target/powerpc/pr108338.c
> index bd83c0b3ad8..5f2f62866ee 100644
> --- a/gcc/testsuite/gcc.target/powerpc/pr108338.c
> +++ b/gcc/testsuite/gcc.target/powerpc/pr108338.c
> @@ -3,9 +3,12 @@
> /* { dg-options "-O2 -save-temps" } */
>
> /* Under lp64, parameter 'v' is in DI regs, then bitcast sub DI to SF. */
> -/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
> -/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
> +/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 2 { target { lp64 && has_arch_pwr8 } } } } */
> +/* { dg-final { scan-assembler-times {\mmtvsrd\M} 2 { target { lp64 && { has_arch_pwr8 && { ! has_arch_pwr9 } } } } } } */
> +/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 && has_arch_pwr9 } } } } */
> +/* { dg-final { scan-assembler-times {\mmtvsrws\M} 1 { target { lp64 && has_arch_pwr9 } } } } */
> /* { dg-final { scan-assembler-times {\mrldicr\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
> +/* { dg-final { scan-assembler-times {\msldi\M} 1 { target { lp64 && { has_arch_pwr8 && { ! has_arch_pwr9 } } } } } } */
>
> struct di_sf_sf
> {
> @@ -22,16 +25,28 @@ sf_from_high32bit_di (struct di_sf_sf v)
> #endif
> }
>
> +float __attribute__ ((noipa))
> +sf_from_low32bit_di (struct di_sf_sf v)
> +{
> +#ifdef __LITTLE_ENDIAN__
> + return v.f1;
> +#else
> + return v.f2;
> +#endif
> +}
> +
> int main()
> {
> struct di_sf_sf v;
> v.f1 = v.f2 = 0.0f;
> #ifdef __LITTLE_ENDIAN__
> + v.f1 = 1.0f;
> v.f2 = 2.0f;
> #else
> v.f1 = 2.0f;
> + v.f2 = 1.0f;
> #endif
> - if (sf_from_high32bit_di (v) != 2.0f)
> + if (sf_from_high32bit_di (v) != 2.0f || sf_from_low32bit_di (v) != 1.0f)
> __builtin_abort ();
> return 0;
> }
> --
> 2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V5 1/2] rs6000: optimize moving to sf from highpart di
2023-10-05 16:52 ` [PATCH V5 1/2] rs6000: optimize moving to sf from highpart di David Edelsohn
@ 2023-10-07 8:01 ` Jiufu Guo
0 siblings, 0 replies; 6+ messages in thread
From: Jiufu Guo @ 2023-10-07 8:01 UTC (permalink / raw)
To: David Edelsohn; +Cc: gcc-patches, segher, linkw, bergner
Hi,
David Edelsohn <dje.gcc@gmail.com> writes:
>
> On Thu, Oct 5, 2023 at 12:50 AM Jiufu Guo <guojiufu@linux.ibm.com> wrote:
>
> Hi,
>
> Currently, we have the pattern "movsf_from_si2" which was trying
> to support moving high part DI to SF.
>
> But current pattern only accepts "ashiftrt":
> XX:SF=bitcast:SF(subreg(YY:DI>>32),0), but actually "lshiftrt" should
> also be ok.
> And current pattern only supports BE.
>
> This patch updats the pattern to support BE and "lshiftrt".
>
> Compare with previous version:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628790.html
> This version refines the code slightly and updates the test case
> according to review comments.
>
> Pass bootstrap and regtest on ppc64{,le}.
> Is this ok for trunk?
>
> Okay.
Thank you! Committed as r14-4444.
BR,
Jeff.
>
> Thanks, David
>
>
> BR,
> Jeff (Jiufu Guo)
>
> PR target/108338
>
> gcc/ChangeLog:
>
> * config/rs6000/predicates.md (lowpart_subreg_operator): New
> define_predicate.
> * config/rs6000/rs6000.md (any_rshift): New code_iterator.
> (movsf_from_si2): Rename to ...
> (movsf_from_si2_<code>): ... this.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/powerpc/pr108338.c: New test.
>
> ---
> gcc/config/rs6000/predicates.md | 5 +++
> gcc/config/rs6000/rs6000.md | 12 ++++---
> gcc/testsuite/gcc.target/powerpc/pr108338.c | 37 +++++++++++++++++++++
> 3 files changed, 49 insertions(+), 5 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108338.c
>
> diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
> index 925f69cd3fc..ef7d3f214c4 100644
> --- a/gcc/config/rs6000/predicates.md
> +++ b/gcc/config/rs6000/predicates.md
> @@ -2098,3 +2098,8 @@ (define_predicate "macho_pic_address"
> else
> return false;
> })
> +
> +(define_predicate "lowpart_subreg_operator"
> + (and (match_code "subreg")
> + (match_test "subreg_lowpart_offset (mode, GET_MODE (SUBREG_REG (op)))
> + == SUBREG_BYTE (op)")))
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 1a9a7b1a479..56bd8bc1147 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -643,6 +643,9 @@ (define_code_iterator any_extend [sign_extend zero_extend])
> (define_code_iterator any_fix [fix unsigned_fix])
> (define_code_iterator any_float [float unsigned_float])
>
> +; Shift right.
> +(define_code_iterator any_shiftrt [ashiftrt lshiftrt])
> +
> (define_code_attr u [(sign_extend "")
> (zero_extend "u")
> (fix "")
> @@ -8303,14 +8306,13 @@ (define_insn_and_split "movsf_from_si"
> ;; {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;}
> ;; split it before reload with "and mask" to avoid generating shift right
> ;; 32 bit then shift left 32 bit.
> -(define_insn_and_split "movsf_from_si2"
> +(define_insn_and_split "movsf_from_si2_<code>"
> [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
> (unspec:SF
> - [(subreg:SI
> - (ashiftrt:DI
> + [(match_operator:SI 3 "lowpart_subreg_operator"
> + [(any_shiftrt:DI
> (match_operand:DI 1 "input_operand" "r")
> - (const_int 32))
> - 0)]
> + (const_int 32))])]
> UNSPEC_SF_FROM_SI))
> (clobber (match_scratch:DI 2 "=r"))]
> "TARGET_NO_SF_SUBREG"
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr108338.c b/gcc/testsuite/gcc.target/powerpc/pr108338.c
> new file mode 100644
> index 00000000000..bd83c0b3ad8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr108338.c
> @@ -0,0 +1,37 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target hard_float } */
> +/* { dg-options "-O2 -save-temps" } */
> +
> +/* Under lp64, parameter 'v' is in DI regs, then bitcast sub DI to SF. */
> +/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
> +/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
> +/* { dg-final { scan-assembler-times {\mrldicr\M} 1 { target { lp64 && has_arch_pwr8 } } } } */
> +
> +struct di_sf_sf
> +{
> + float f1; float f2; long long l;
> +};
> +
> +float __attribute__ ((noipa))
> +sf_from_high32bit_di (struct di_sf_sf v)
> +{
> +#ifdef __LITTLE_ENDIAN__
> + return v.f2;
> +#else
> + return v.f1;
> +#endif
> +}
> +
> +int main()
> +{
> + struct di_sf_sf v;
> + v.f1 = v.f2 = 0.0f;
> +#ifdef __LITTLE_ENDIAN__
> + v.f2 = 2.0f;
> +#else
> + v.f1 = 2.0f;
> +#endif
> + if (sf_from_high32bit_di (v) != 2.0f)
> + __builtin_abort ();
> + return 0;
> +}
> --
> 2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-10-07 8:01 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2023-10-05 4:13 [PATCH V5 1/2] rs6000: optimize moving to sf from highpart di Jiufu Guo
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2023-10-05 16:54 ` David Edelsohn
2023-10-07 8:00 ` Jiufu Guo
2023-10-05 16:52 ` [PATCH V5 1/2] rs6000: optimize moving to sf from highpart di David Edelsohn
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